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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dsamsung,exynos850-clock.yaml20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
165 - description: External reference clock (26 MHz)
183 - description: External reference clock (26 MHz)
201 - description: External reference clock (26 MHz)
225 - description: External reference clock (26 MHz)
[all …]
Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
70 - description: External reference clock (26 MHz)
86 - description: External reference clock (26 MHz)
104 - description: External reference clock (26 MHz)
122 - description: External reference clock (26 MHz)
142 - description: External reference clock (26 MHz)
164 - description: External reference clock (26 MHz)
186 - description: External reference clock (26 MHz)
206 - description: External reference clock (26 MHz)
226 - description: External reference clock (26 MHz)
Dsamsung,exynos7885-clock.yaml20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
64 - description: External reference clock (26 MHz)
80 - description: External reference clock (26 MHz)
102 - description: External reference clock (26 MHz)
128 - description: External reference clock (26 MHz)
/kernel/linux/linux-5.10/drivers/net/wireless/ti/wl12xx/
Dwl12xx.h73 WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
83 WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
85 WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
86 WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/ti/wl12xx/
Dwl12xx.h73 WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
83 WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
85 WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
86 WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */
[all …]
/kernel/linux/linux-5.10/drivers/media/tuners/
Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
45 1e 00 ? looks like operation register; write cmd here, read result from 1f-26
53 26 08 ?
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/kernel/linux/linux-6.6/drivers/media/tuners/
Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
45 1e 00 ? looks like operation register; write cmd here, read result from 1f-26
53 26 08 ?
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/kernel/linux/linux-6.6/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
91 # 26 chars 29 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
[all …]
/kernel/linux/linux-5.10/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
91 # 26 chars 29 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/fw/api/
Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/
Dmax8952.txt15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/fw/api/
Drs.h70 * bandwidths <= 80MHz
72 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
91 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
92 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
93 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
94 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
191 * pair (0 - 80mhz width and below, 1 - 160mhz).
314 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
316 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
318 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/regulator/
Dmaxim,max8952.yaml62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/ufs/
Dufshcd-pltfrm.txt42 specification allows host to provide one of the 4 frequencies (19.2 MHz,
43 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
45 Defaults to 26 MHz(as per specification) if not specified by host.
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
121 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
130 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
146 /* TIMER0 runs directly on the 25MHz chrystal */
152 /* TIMER1 runs @ 1MHz */
158 /* TIMER2 runs @ 1MHz */
176 /* The SIC is cascaded off IRQ 26 on the PIC */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/arm/
Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
179 /* The SIC is cascaded off IRQ 26 on the PIC */
[all …]
/kernel/linux/linux-5.10/drivers/phy/ti/
Dphy-ti-pipe3.c84 #define MEM_OVRD_HS_RATE BIT(26)
85 #define MEM_OVRD_HS_RATE_SHIFT 26
186 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
187 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
188 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
189 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
190 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
191 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
196 {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
197 {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
[all …]
/kernel/linux/linux-6.6/drivers/phy/ti/
Dphy-ti-pipe3.c84 #define MEM_OVRD_HS_RATE BIT(26)
85 #define MEM_OVRD_HS_RATE_SHIFT 26
186 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
187 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
188 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
189 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
190 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
191 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
196 {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
197 {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml68 mediatek,src-ref-clk-mhz:
71 default: 26
94 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
176 mediatek,src-ref-clk-mhz = <26>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Dtoshiba,tc358767.txt8 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-mt65xx.txt27 - <&clk26m>: specify parent clock 26MHZ.
28 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
30 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
31 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
32 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dstmpe.txt28 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz
29 1 -> 3.25 MHz
36 interrupts = <26 0x4>;
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk-tegra30.c32 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
33 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
34 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
35 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
187 { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */
192 { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */
199 { 26000000, 624000000, 624, 26, 1, 8 },
204 { 26000000, 600000000, 600, 26, 1, 8 },
207 { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
209 { 26000000, 520000000, 520, 26, 1, 8 },
[all …]
/kernel/linux/linux-6.6/drivers/clk/tegra/
Dclk-tegra30.c34 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
35 #define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
36 #define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
37 #define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
189 { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */
194 { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */
201 { 26000000, 624000000, 624, 26, 1, 8 },
206 { 26000000, 600000000, 600, 26, 1, 8 },
209 { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
211 { 26000000, 520000000, 520, 26, 1, 8 },
[all …]
/kernel/linux/linux-6.6/include/media/i2c/
Dtc358743.h33 u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */
61 * bps pr lane is 823.5 MHz, and can serve as a starting point.
86 /* Reset PHY automatically when TMDS clock passes 21 MHz.

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