Home
last modified time | relevance | path

Searched full:297 (Results 1 – 25 of 238) sorted by relevance

12345678910

/kernel/linux/linux-6.6/arch/sparc/include/asm/
Dvisasm.h18 be,pt %icc, 297f; \
19 sethi %hi(297f), %g7; \
22 or %g7, %lo(297f), %g7; \
23 297: wr %g0, FPRS_FEF, %fprs; \
40 be,pt %icc, 297f; \
43 297: wr %o5, FPRS_FEF, %fprs;
/kernel/linux/linux-5.10/arch/sparc/include/asm/
Dvisasm.h18 be,pt %icc, 297f; \
19 sethi %hi(297f), %g7; \
22 or %g7, %lo(297f), %g7; \
23 297: wr %g0, FPRS_FEF, %fprs; \
40 be,pt %icc, 297f; \
43 297: wr %o5, FPRS_FEF, %fprs;
/kernel/linux/linux-6.6/drivers/clk/hisilicon/
Dcrg-hi3516cv300.c50 { HI3516CV300_FIXED_297M, "297m", NULL, 0, 297000000, },
56 "24m", "83.3m", "148.5m", "198m", "297m"
/kernel/linux/linux-5.10/drivers/clk/hisilicon/
Dcrg-hi3516cv300.c50 { HI3516CV300_FIXED_297M, "297m", NULL, 0, 297000000, },
56 "24m", "83.3m", "148.5m", "198m", "297m"
/kernel/linux/linux-6.6/arch/sparc/kernel/syscalls/
Dsyscall.tbl361 297 32 pselect6 sys_pselect6_time32 compat_sys_pselect6_time32
362 297 64 pselect6 sys_pselect6
/kernel/linux/linux-5.10/arch/sparc/kernel/syscalls/
Dsyscall.tbl361 297 32 pselect6 sys_pselect6_time32 compat_sys_pselect6_time32
362 297 64 pselect6 sys_pselect6
/kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/
Drcar_dw_hdmi.c46 * The maximum supported clock frequency is 297 MHz, as shown in the PHY in rcar_hdmi_mode_valid()
/kernel/linux/linux-6.6/drivers/gpu/drm/renesas/rcar-du/
Drcar_dw_hdmi.c46 * The maximum supported clock frequency is 297 MHz, as shown in the PHY in rcar_hdmi_mode_valid()
/kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/
Dia_css_ctc_table.host.c38 321, 318, 312, 308, 304, 300, 297, 294,
/kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/
Dia_css_ctc_table.host.c38 321, 318, 312, 308, 304, 300, 297, 294,
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dexynos5250.h100 #define CLK_I2C3 297
Dtegra194-clock.h292 #define TEGRA194_CLK_PVA0_VPS 297
Dqcom,gcc-mdm9615.h307 #define USB_HS3_XCVR_CLK 297
Dtegra30-car.h262 /* 297 */
Dqcom,gcc-msm8960.h305 #define USB_HS3_XCVR_CLK 297
Dexynos4.h135 #define CLK_SDMMC0 297
Dqcom,gcc-msm8974.h306 #define GCC_CE1_AXI_CLK_SLEEP_ENA 297
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dexynos5250.h101 #define CLK_I2C3 297
Dqcom,gcc-mdm9615.h307 #define USB_HS3_XCVR_CLK 297
Dtegra194-clock.h292 #define TEGRA194_CLK_PVA0_VPS 297
Dexynos4.h135 #define CLK_SDMMC0 297
Dtegra30-car.h262 /* 297 */
Dqcom,gcc-msm8960.h305 #define USB_HS3_XCVR_CLK 297
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Drenesas,r8a779f0-ether-switch.yaml190 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
/kernel/linux/linux-6.6/include/dt-bindings/arm/
Dqcom,ids.h148 #define QCOM_ID_MDM9207 297

12345678910