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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/aarch64/
Daarch64_imm_valid.h7 * http://www.apache.org/licenses/LICENSE-2.0
27 uint64 mask2 = (1UL << static_cast<uint64>(nLowerZeroBits)) - 1UL; in IsBitSizeImmediate()
47 // get lower 32 bits in IsMoveWidableImmediateCopy()
49 …// If lower 32 bits are all 0, but higher 32 bits have 1, val will be 1 and return true, but it is… in IsMoveWidableImmediateCopy()
65 // When value & ffffffff00000000 is 0, all high 32-bits are 0. in IsSingleInstructionMovable32()
66 // When value & ffffffff00000000 is ffffffff00000000, all high 32-bits are 1. in IsSingleInstructionMovable32()
67 // High 32-bits should be all 0 or all 1, when it comes to mov w0, #imm. in IsSingleInstructionMovable32()
72 constexpr uint32 bitLen = 32; in IsSingleInstructionMovable32()
89 // for target linux-aarch64-gnu in Imm12BitValid()
94 // For the 32-bit variant: is the bitmask immediate
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Daarch64_int_regs.def7 * http://www.apache.org/licenses/LICENSE-2.0
27 * to it as WZR in a 32-bit context or XZR in a 64-bit context.
31 /* ID, 32-bit prefix, 64-bit prefix, canBeAssigned, isCalleeSave, isParam, isSpill, isExtraSpill */
66 * We should not use "W" prefix in 64-bit context, though!!
71 /* Alias ID, ID, 32-bit prefix, 64-bit prefix */
/arkcompiler/runtime_core/static_core/plugins/ets/templates/stdlib/
DDataView.ets.j22 * Copyright (c) 2021-2025 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
47 this(buffer, byteOffset, (buffer as Buffer).getByteLength() - byteOffset)
76 …teOffset, 0), asIntOrDefault(byteLength, (buffer as Buffer).getByteLength() - asIntOrDefault(byteO…
79 {%- for bit in [8, 16, 32, 64] %}
80 {%- for mode in ["Int", "Uint", "Float"] %}
81 {%- if mode != "Float" or bit >= 32 %}
82 // === {{mode}}{{bit}} ===
83 {%- set impls = ['Little', 'Big'] if bit != 8 else ['Big'] %}
85 {%- set type2nameBits = {8: "byte", 16: "short", 32: "int", 64: "long"} %}
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/arkcompiler/runtime_core/compiler/docs/
Dinterface_inline_cache.md11 * There is a 90% - 95% chance that the same method will be used in real-world application test.
20 * must be 64bit system
27 Cache structure:（offset addr)/(class addr) 32bit/32bit
28 -----------------------------------------------
31 cache:offset/class ---------->| <-|
35 --> call runtime irtoc function | |
36 read cache <-----------------------| |
41 save method‘s offset to cache >------|
42 <-- return to (.text)
44 -----------------------------------------------
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/arkcompiler/runtime_core/static_core/compiler/docs/
Dinterface_inline_cache.md11 * There is a 90% - 95% chance that the same method will be used in real-world application test.
20 * must be 64bit system
27 Cache structure:（offset addr)/(class addr) 32bit/32bit
28 -----------------------------------------------
31 cache:offset/class ---------->| <-|
35 --> call runtime irtoc function | |
36 read cache <-----------------------| |
41 save method‘s offset to cache >------|
42 <-- return to (.text)
44 -----------------------------------------------
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/arkcompiler/runtime_core/static_core/plugins/ets/tests/ets_sdk/arkts/@arkts/collections/BitVector/
DhasTests.ets7 * http://www.apache.org/licenses/LICENSE-2.0
25 …suite.addTest("Verify if bit vector correctly identifies bit values within a specified range.", Bi…
26 …suite.addTest("Verify that bit vector throws an error when toIndex is negative.", BitVector_has_Fu…
27 …suite.addTest("Verify that bit vector throws an error when fromIndex is not an integer.", BitVecto…
28 …suite.addTest("Verify that bit vector throws an error when both fromIndex and toIndex are negative…
29 …suite.addTest("Verify that bit vector throws an error when fromIndex is negative while toIndex is …
30 …suite.addTest("Verify if bit vector correctly identifies bit values in a large range spanning mult…
31 …suite.addTest("Verify if bit vector with initial length correctly identifies bit values across its…
32 …suite.addTest("Verify that bit vector throws an error when fromIndex is greater than toIndex.", Bi…
33 …suite.addTest("Verify if bit vector correctly identifies bit values in a single-element range.", B…
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DsetBitsByRangeTests.ets7 * http://www.apache.org/licenses/LICENSE-2.0
25 …suite.addTest("Verify setting a range of bits updates the bit vector correctly.", BitVector_setBit…
30 …suite.addTest("Verify setting a large range of bits updates the bit vector correctly.", BitVector_…
31 …suite.addTest("Verify setting a range of bits with an initial offset updates the bit vector correc…
39 * @tc.desc : Verify setting a range of bits to 0 and 1 updates the bit vector correctly.
52 assertEQ(bitVector[1], 0, "Bit at index 1 should be 0");
53 assertEQ(bitVector[2], 0, "Bit at index 2 should be 0");
54 assertEQ(bitVector[3], 0, "Bit at index 3 should be 0");
56 assertEQ(bitVector[1], 1, "Bit at index 1 should be 1");
57 assertEQ(bitVector[2], 1, "Bit at index 2 should be 1");
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DgetBitCountByRangeTests.ets7 * http://www.apache.org/licenses/LICENSE-2.0
25 …suite.addTest("Counts the occurrences of a bit element within a valid range.", BitVector_getBitCou…
27 …suite.addTest("Throws an error for non-integer 'fromIndex'.", BitVector_getBitCountByRange_Func_00…
30 …suite.addTest("Counts the occurrences of a bit element in a large range.", BitVector_getBitCountBy…
31 …suite.addTest("Counts the occurrences of a bit element with an initial length.", BitVector_getBitC…
39 * @tc.desc : Counts the occurrences of a bit element within a valid range in a bit vector.
51 …ssertEQ(bitVector.getBitCountByRange(0, 0, 5), 3, "BitVector should contain 3 zeros in range 0-5");
52 …assertEQ(bitVector.getBitCountByRange(1, 0, 5), 2, "BitVector should contain 2 ones in range 0-5");
76 …sage === `The value of "toIndex" is out of range. It must be >= 0 && <= 8. Received value is: -3`);
78 expectThrow(() => { bitVector.getBitCountByRange(0, 8, -3); }, exceptionCheck);
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DflipBitByIndexTests.ets7 * http://www.apache.org/licenses/LICENSE-2.0
25 …suite.addTest("Verify basic bit flipping functionality in a bit vector.", BitVector_flipBitByIndex…
27 …suite.addTest("Test flipBitByIndex with non-integer index value.", BitVector_flipBitByIndex_Func_0…
28 …suite.addTest("Test bit flipping operations on larger bit vector.", BitVector_flipBitByIndex_Func_…
29 …suite.addTest("Test bit flipping operations on bit vector with initial size.", BitVector_flipBitBy…
37 * @tc.desc : Test flipping bits from 1 to 0 and from 0 to 1 in a bit vector.
54 assertEQ(bitVector[0], 0, "Bit at index 0 should be flipped to 0");
55 assertEQ(bitVector[1], 0, "Bit at index 1 should be flipped to 0");
56 assertEQ(bitVector[2], 0, "Bit at index 2 should be flipped to 0");
57 assertEQ(bitVector[3], 0, "Bit at index 3 should be flipped to 0");
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/arkcompiler/runtime_core/static_core/libpandabase/utils/
Dregmask.h2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
44 size_t res = (1ULL << width) - 1; in MakeMaskByExcluding()
50 * Base struct for registers mask, template-parametrized by number of registers.
51 * Currently we don't support registers number greater than 32.
59 // We don't support architectures with CPU registers number, greater than 32.
67 // NOLINTNEXTLINE(google-explicit-constructor)
90 constexpr bool Test(size_t bit) const in Test() argument
92 ASSERT(bit < Size()); in Test()
93 return ((value_ >> static_cast<ValueType>(bit)) & 1U) != 0; in Test()
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/arkcompiler/runtime_core/libpandabase/utils/
Dregmask.h2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
44 size_t res = (1ULL << width) - 1; in MakeMaskByExcluding()
50 * Base struct for registers mask, template-parametrized by number of registers.
51 * Currently we don't support registers number greater than 32.
59 // We don't support architectures with CPU registers number, greater than 32.
67 // NOLINTNEXTLINE(google-explicit-constructor)
90 constexpr bool Test(size_t bit) const in Test() argument
92 ASSERT(bit < Size()); in Test()
93 return ((value_ >> static_cast<ValueType>(bit)) & 1U) != 0; in Test()
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/arkcompiler/runtime_core/static_core/verification/util/
Dmem.h2 * Copyright (c) 2022-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
24 is unavailable for allocation -- for example, it may be reserved for kernel memory.
27 https://linux-kernel-labs.github.io/refs/heads/master/lectures/address-space.html
29 Linux is using a split address space for 32 bit systems, although in the past there
31 …architecture that supports it, e.g. x86). Linux always uses split address space for 64 bit systems.
33 [For 32-bit Linux, the split is usually 3/1, i.e. 0x00000000-0xc0000000 is user space,
34 0xc0000000-0xffffffff is kernel space]
36 …For Windows: https://learn.microsoft.com/en-us/windows-hardware/drivers/gettingstarted/virtual-add…
38 For a 32-bit process, the virtual address space is usually the 2-gigabyte range 0x00000000
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/arkcompiler/ets_runtime/ecmascript/jspandafile/
Dconstpool_value.h7 * http://www.apache.org/licenses/LICENSE-2.0
64 // NOLINTNEXTLINE(readability-magic-numbers)
65 using ConstPoolIndexField = BitField<uint32_t, 0, 32>; // 32: 32 bit
66 // NOLINTNEXTLINE(readability-magic-numbers)
67 using ConstPoolTypeField = BitField<ConstPoolType, 32, 4>; // 32: offset, 4: 4bit
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_ir/include/
Dcmpl.h7 * http://www.apache.org/licenses/LICENSE-2.0
36 uint8 *formalWordsTypetagged; // bit vector where the Nth bit tells whether
43 uint8 *localWordsTypetagged; // bit vector where the Nth bit tells whether
46 // the word at location (%%FP - N*4)) has
48 // at (%%FP - N*4 + 4); the bitvector's size
50 uint8 *formalWordsRefCounted; // bit vector where the Nth bit tells whether
57 uint8 *localWordsRefCounted; // bit vector where the Nth bit tells whether
60 // the word at location (%%FP - N*4)) points to
76 return funcSize - (kTwoBitVectors * BlockSize2BitVectorSize(upFormalSize)) - in FuncCodeSize()
89 uint8 *globalWordsTypetagged; // bit vector where the Nth bit tells whether
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/arkcompiler/runtime_core/static_core/runtime/mem/gc/g1/
Dg1-helpers.cpp2 * Copyright (c) 2023-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
19 #include "runtime/mem/gc/g1/g1-helpers.h"
20 #include "runtime/mem/gc/card_table-inl.h"
28 GCBarrierSet *barrierSet = thread->GetBarrierSet(); in GetG1BarrierSet()
35 // The cast below is needed to truncate high 32bits from 64bit pointer in PreWrbFuncEntrypoint()
36 // in case object pointers have 32bit. in PreWrbFuncEntrypoint()
39 … ASSERT(IsAddressInObjectsHeap(static_cast<const ObjectHeader *>(oldval)->ClassAddr<BaseClass>())); in PreWrbFuncEntrypoint()
42 …// thread can't be null here because pre-barrier is called only in concurrent-mark, but we don't p… in PreWrbFuncEntrypoint()
43 // weak-references in concurrent mark in PreWrbFuncEntrypoint()
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/
Delf_types.h7 * http://www.apache.org/licenses/LICENSE-2.0
33 #define ELFCLASS64 2 /* 64-bit objects */
42 #define EM_X86_64 62 /* AMD x86-64 architecture */
45 #define R_AARCH64_ADR_PREL_PG_HI21 275 /* Page-rel. ADRP imm. from 32:12. */
48 #define R_X86_64_32 10 /* Direct 32 bit zero extended */
49 #define R_X86_64_64 1 /* Direct 64 bit */
51 #define R_X86_64_PC32 2 /* PC relative 32 bit signed */
52 #define R_X86_64_PC64 24 /* PC relative 64 bit */
53 #define R_X86_64_PLT32 4 /* 32 bit PLT address */
58 #define SHF_MASKPROC 0xf0000000 /* Processor-specific */
/arkcompiler/runtime_core/static_core/docs/
Dcode_metainfo.md5 Metainfo is an information that aims to provide reg-to-stack mapping for virtual registers. It is n…
14 +-------------+
16 | +-------------------+
20 +-------------+-------------------+
21 | | <-- Method::CompiledCodeEntrypoint
24 +-------------+-----------------+
26 | |-----------------+----------------------+
31 | | Bit Tables | Method indexes |
37 |-------------+-----------------+----------------------+
40 ## Bit table
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/arkcompiler/runtime_core/docs/
Dcode_metainfo.md5 Metainfo is an information that aims to provide reg-to-stack mapping for virtual registers. It is n…
14 +-------------+
16 | +-------------------+
20 +-------------+-------------------+
21 | | <-- Method::CompiledCodeEntrypoint
24 +-------------+-----------------+
26 | |-----------------+----------------------+
31 | | Bit Tables | Method indexes |
37 |-------------+-----------------+----------------------+
40 ## Bit table
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/arkcompiler/runtime_core/compiler/optimizer/ir/
Dinstructions.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
19 Describes signature of the instruction. Properties of the operands are separated by '-' symbol.
39 - equal_common_types
40 - float_src_eq_dst_size
41 - integer_src_ge_dst_size
43 - equal_common_types
44 - integer_src_ge_dst_size
46 - equal_common_types
47 - integer_src_ge_dst_size
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/arkcompiler/runtime_core/static_core/libpandabase/tests/
Dregmask_test.cpp2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
29 …ASSERT_EQ(mask.GetMaxRegister(), base.size() - Clz(static_cast<RegMask::ValueType>(base.to_ulong()… in CompareWithBitset()
61 void TestDistance(RegMask mask, size_t bit, size_t bitsBefore, size_t bitsAfter) in TestDistance() argument
63 ASSERT_EQ(mask.GetDistanceFromTail(bit), bitsBefore); in TestDistance()
64 ASSERT_EQ(mask.GetDistanceFromHead(bit), bitsAfter); in TestDistance()
69 // NOLINTBEGIN(readability-magic-numbers) in TEST()
72 TestRegMask(MakeMaskByExcluding(32U, 0U)); in TEST()
73 TestRegMask(MakeMaskByExcluding(32U, 31U)); in TEST()
74 TestRegMask(MakeMaskByExcluding(32U, 0U, 31U)); in TEST()
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/arkcompiler/runtime_core/libpandabase/tests/
Dregmask_test.cpp2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
29 …ASSERT_EQ(mask.GetMaxRegister(), base.size() - Clz(static_cast<RegMask::ValueType>(base.to_ulong()… in CompareWithBitset()
61 void TestDistance(RegMask mask, size_t bit, size_t bits_before, size_t bits_after) in TestDistance() argument
63 ASSERT_EQ(mask.GetDistanceFromTail(bit), bits_before); in TestDistance()
64 ASSERT_EQ(mask.GetDistanceFromHead(bit), bits_after); in TestDistance()
71 TestRegMask(MakeMaskByExcluding(32, 0));
72 TestRegMask(MakeMaskByExcluding(32, 31));
73 TestRegMask(MakeMaskByExcluding(32, 0, 31));
74 TestRegMask(MakeMaskByExcluding(32, 0, 15, 31));
/arkcompiler/runtime_core/docs/changelogs/
D2022-08-18-isa-changelog.md1 # 2022-08-18-isa-changelog
15 3. We add prefix "deprecated" and keep the many old isa as "deprecated"-prefixed opcodes (for compa…
20 8. We add 8-bit or 16-bit imm as inline cache slot for some specific opcodes.
23 As we merge some "define-function" opcodes as one opcode, in function we add one field which record…
24 such that runtime can distinguish the "define-function" operations of different kinds.
26 We reuse the field 32-bit field `access_flags_` to encode Function Kind and Header index.
27 This will not introduce compatibility issue because the later 24-bit of `access_flags_` is unused i…
30 |<- 16-bit header index ->|<- 8-bit function kind ->|<- 8-bit original access flag ->|
39 As we use 16-bit to encode methodId, stringId and literalarrayId, the number of these Ids in one me…
45 3. In bytecode, we still use 16-bit literalarrayId rather than offset.
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/arkcompiler/runtime_core/static_core/isa/
Disa.yaml1 # Copyright (c) 2021-2025 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
14 ---
17 - name: General Design
19 …VM is register-based with a dedicated accumulator register that serves as an implicit operand to i…
21 - name: Registers
31 - name: Accumulator
37 …Moreover, when an instruction has more than one source operand, the shorter-living value must be p…
39 …dvantage. For example, arguments for the`call.range` instruction can be moved register-to-register.
41 - name: Calling Sequence
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/arkcompiler/runtime_core/static_core/runtime/include/
Dobject_header.h2 * Copyright (c) 2021-2025 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
16 // - Get/Set Mark or Class word
17 // - Get size of the object header and an object itself
18 // - Get/Generate an object hash
20 // - Get different object fields
21 // - Return object type
22 // - Verify object
23 // - Is it a subclass of not
24 // - Get field addr
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/arkcompiler/runtime_core/static_core/runtime/bridge/arch/arm/
Dcompiled_code_to_interpreter_bridge_arm.S2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
36 // store r0-r3 before the frame to make arg array continuos with stack args
37 push {r0-r3}
49 CFI_ADJUST_CFA_OFFSET(-4)
57 push {r4 - r10}
58 CFI_REL_OFFSET(r10, -(2 * 4))
59 CFI_REL_OFFSET(r9, -(3 * 4))
60 CFI_REL_OFFSET(r8, -(4 * 4))
61 CFI_REL_OFFSET(r7, -(5 * 4))
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