Home
last modified time | relevance | path

Searched +full:32 +full:khz (Results 1 – 25 of 1076) sorted by relevance

12345678910>>...44

/kernel/linux/linux-6.6/Documentation/fb/
Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
30 geometry 640 480 640 480 32
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
[all …]
/kernel/linux/linux-5.10/Documentation/fb/
Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
30 geometry 640 480 640 480 32
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherals to enable low
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 32 kHz Oscillator
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherials to enable low
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 32 kHz Oscillator
Damlogic,gxbb-aoclkc.txt19 * "ext-32k-0" : external 32kHz reference #0 if any (optional)
20 * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
21 * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
/kernel/linux/linux-5.10/drivers/video/fbdev/core/
Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
43 { NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 0,
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
55 { NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
66 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
[all …]
/kernel/linux/linux-6.6/drivers/video/fbdev/core/
Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
43 { NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 0,
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
55 { NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
66 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap1/
Dtimer32k.c4 * OMAP 32K Timer
53 #include <plat/counter-32k.h>
61 * 32KHz OS timer
64 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
65 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
67 * with the 32KHz synchronized timer.
131 .name = "32k-timer",
154 IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL)) in omap_init_32k_timer()
155 pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER); in omap_init_32k_timer()
177 pr_err("32k_counter: failed to map base addr\n"); in omap_32k_timer_init()
/kernel/linux/linux-6.6/arch/arm/mach-omap1/
Dtimer32k.c4 * OMAP 32K Timer
59 * 32KHz OS timer
62 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
63 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
65 * with the 32KHz synchronized timer.
129 .name = "32k-timer",
152 IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL)) in omap_init_32k_timer()
153 pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER); in omap_init_32k_timer()
160 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
167 * 32KHz clocksource ... always available, on pretty most chips except
[all …]
DKconfig68 bool "Use 32KHz timer"
72 Select this option if you want to enable the OMAP 32KHz timer.
74 support for no tick during idle. The 32KHz timer provides less
75 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
88 timer provides more intra-tick resolution than the 32KHz timer,
/kernel/linux/linux-5.10/arch/arm/plat-omap/
DKconfig72 timer provides more intra-tick resolution than the 32KHz timer,
76 bool "Use 32KHz timer"
80 Select this option if you want to enable the OMAP 32KHz timer.
82 support for no tick during idle. The 32KHz timer provides less
83 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
/kernel/linux/linux-5.10/Documentation/arm/sunxi/
Dclocks.rst18 24MHz 32kHz
26 When you are about to suspend, you switch the CPU Mux to the 32kHz
29 24Mhz 32kHz
39 32kHz
/kernel/linux/linux-6.6/Documentation/arch/arm/sunxi/
Dclocks.rst18 24MHz 32kHz
26 When you are about to suspend, you switch the CPU Mux to the 32kHz
29 24Mhz 32kHz
39 32kHz
/kernel/linux/linux-6.6/include/sound/
Demu10k1.h28 #define MAXPAGES0 4096 /* 32 bit mode */
35 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
209 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
210 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
597 // 32 cache registers (== 128 bytes) per channel follow.
605 // The engine has a fetch threshold of 32 bytes, so it tries to keep
607 // 8-bit stereo), or 32 (8-bit mono). The actual transfers are pretty
630 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
631 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
632 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
[all …]
Dasoundef.h27 #define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */
28 #define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */
29 #define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */
114 #define IEC958_AES3_CON_FS_44100 (0<<0) /* 44.1kHz */
116 #define IEC958_AES3_CON_FS_48000 (2<<0) /* 48kHz */
117 #define IEC958_AES3_CON_FS_32000 (3<<0) /* 32kHz */
118 #define IEC958_AES3_CON_FS_22050 (4<<0) /* 22.05kHz */
119 #define IEC958_AES3_CON_FS_24000 (6<<0) /* 24kHz */
120 #define IEC958_AES3_CON_FS_88200 (8<<0) /* 88.2kHz */
121 #define IEC958_AES3_CON_FS_768000 (9<<0) /* 768kHz */
[all …]
Ddesignware_i2s.h15 * @data_width: number of bits per sample (8/16/24/32 bit)
16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
/kernel/linux/linux-5.10/include/sound/
Demu10k1.h29 #define MAXPAGES0 4096 /* 32 bit mode */
39 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
178 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
179 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
587 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
588 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
589 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
590 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
591 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
592 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
[all …]
Ddesignware_i2s.h15 * @data_width: number of bits per sample (8/16/24/32 bit)
16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
Dasoundef.h27 #define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */
28 #define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */
29 #define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */
114 #define IEC958_AES3_CON_FS_44100 (0<<0) /* 44.1kHz */
116 #define IEC958_AES3_CON_FS_48000 (2<<0) /* 48kHz */
117 #define IEC958_AES3_CON_FS_32000 (3<<0) /* 32kHz */
118 #define IEC958_AES3_CON_FS_22050 (4<<0) /* 22.05kHz */
119 #define IEC958_AES3_CON_FS_24000 (6<<0) /* 24kHz */
120 #define IEC958_AES3_CON_FS_88200 (8<<0) /* 88.2kHz */
121 #define IEC958_AES3_CON_FS_768000 (9<<0) /* 768kHz */
[all …]
/kernel/linux/linux-5.10/drivers/cpufreq/
Dtegra194-cpufreq.c21 #define KHZ 1000 macro
25 #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
72 * [63:32] Core clock counter: counts on every core clock cycle
87 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
97 * ref_clk_counter(32 bit counter) runs on constant clk, in tegra_read_counters()
99 * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter in tegra_read_counters()
102 * Like wise core_clk_counter(32 bit counter) runs on core clock. in tegra_read_counters()
105 * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter in tegra_read_counters()
130 * - Return Kcycles/second, freq in KHz
137 * in KHz = (delta cycles * 408 * 10^3) / delta ref_clk_counter
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-ep93xx/
Dtimer-ep93xx.c18 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
19 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
22 * The 508 kHz timers are ideal for use for the timer interrupt, as the
23 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
60 ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); in ep93xx_read_sched_clock()
69 ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); in ep93xx_clocksource_read()
76 /* Default mode: periodic, off, 508 kHz */ in ep93xx_clkevt_set_next_event()
/kernel/linux/linux-6.6/arch/arm/mach-ep93xx/
Dtimer-ep93xx.c18 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
19 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
22 * The 508 kHz timers are ideal for use for the timer interrupt, as the
23 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
60 ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); in ep93xx_read_sched_clock()
69 ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); in ep93xx_clocksource_read()
76 /* Default mode: periodic, off, 508 kHz */ in ep93xx_clkevt_set_next_event()
/kernel/linux/linux-5.10/sound/ppc/
Dawacs.h112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
116 #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */
117 #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */
118 #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */
119 #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
172 #define RATE_48000 (0x0 << 8) /* 48 kHz */
173 #define RATE_44100 (0x0 << 8) /* 44.1 kHz */
[all …]
/kernel/linux/linux-6.6/sound/ppc/
Dawacs.h112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
116 #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */
117 #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */
118 #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */
119 #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
172 #define RATE_48000 (0x0 << 8) /* 48 kHz */
173 #define RATE_44100 (0x0 << 8) /* 44.1 kHz */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dmax77620.txt36 with internal regulators. 32KHz clock can be programmed to be part of a
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
58 and 32KHz clock get disabled at
68 regulators, GPIOs and 32kHz clocks are provided in their respective

12345678910>>...44