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Searched +full:3 +full:e3 (Results 1 – 25 of 290) sorted by relevance

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/kernel/linux/linux-5.10/arch/mips/include/asm/txx9/
D	tx3927.h	`19 #define TX3927_NR_TMR 3 27 volatile unsigned long tr[3]; 58 #define endian_def_sb2(e1, e2, e3) \ argument 59 volatile unsigned short e1;volatile unsigned char e2, e3 60 #define endian_def_b2s(e1, e2, e3) \ argument 61 volatile unsigned char e1, e2;volatile unsigned short e3 62 #define endian_def_b4(e1, e2, e3, e4) \ argument 63 volatile unsigned char e1, e2, e3, e4 67 #define endian_def_sb2(e1, e2, e3) \ argument 68 volatile unsigned char e3, e2;volatile unsigned short e1 [all …]`
/kernel/linux/linux-6.6/drivers/edac/
D	ie31200_edac.c	3 * Intel E3-1200 6 * Support for the E3-1200 processor family. Heavily based on previous 14 * 0108: Xeon E3-1200 Processor Family DRAM Controller 15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller 16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller 18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller 20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller 21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers [all …]
/kernel/linux/linux-6.6/arch/m68k/fpsp040/
D	x_ovfl.S	`77 btstb #E3,E_BYTE(%a6) 79 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 100 \| andi.b #$3,%d0 107 btstb #E3,E_BYTE(%a6) 109 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 124 bclrb #E3,E_BYTE(%a6) \|test and clear E3 bit 130 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 156 btstb #E3,E_BYTE(%a6) \|test E3 bit 169 cmpiw #3,%d0 \|check for opclass3`
D	x_unfl.S	`61 btstb #E3,E_BYTE(%a6) 67 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 95 btstb #E3,E_BYTE(%a6) 101 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 116 bclrb #E3,E_BYTE(%a6) 122 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 151 \| If the exception bit set is E3, the exceptional operand from the 154 btstb #E3,E_BYTE(%a6) 232 \| ;double $3ff $3fe`
D	gen_except.S	`80 bfextu CMDREG1B(%a6){#10:#3},%d1 \|extract bit 3,4,5 168 \| exception is to set the E1/E3 byte and clr the U flag. 170 \| operr, and dz. commonE3 does this for E3 exceptions, which 182 bsetb #E3,E_BYTE(%a6) \|set E3 flag 190 bsetb #E3,E_BYTE(%a6) \|set E3 flag 199 bfextu CMDREG1B(%a6){#10:#3},%d1 \|extract bit 3,4,5 300 bsetb #E3,E_BYTE(%a6) \|set E3 flag 311 bfextu CMDREG1B(%a6){#10:#3},%d1 \|extract bit 3,4,5 319 \| NOTE * Bug fix for errata (0d43b #3)`
D	util.S	`103 btstb #E3,E_BYTE(%a6) \|check for nu exception 159 \| This entry point used by x_ovfl. (opclass 3 only) 182 lsll #2,%d0 \|move round precision to d0{3:2} 184 orl %d1,%d0 \|index is fmt:mode in d0{3:0} 328 \| if E3 355 btstb #E3,E_BYTE(%a6) 423 btstb #E3,E_BYTE(%a6) 426 clrl %d0 \|if E3, only opclass 0x0 is possible 430 bfextu %d0{#0:#3},%d0 \|shift opclass bits d0{31:29} to d0{2:0} 436 \| If E3, the format is extended. [all …]`
/kernel/linux/linux-5.10/arch/m68k/fpsp040/
D	x_ovfl.S	`77 btstb #E3,E_BYTE(%a6) 79 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 100 \| andi.b #$3,%d0 107 btstb #E3,E_BYTE(%a6) 109 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 124 bclrb #E3,E_BYTE(%a6) \|test and clear E3 bit 130 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 156 btstb #E3,E_BYTE(%a6) \|test E3 bit 169 cmpiw #3,%d0 \|check for opclass3`
D	x_unfl.S	`61 btstb #E3,E_BYTE(%a6) 67 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 95 btstb #E3,E_BYTE(%a6) 101 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 116 bclrb #E3,E_BYTE(%a6) 122 bfextu CMDREG3B(%a6){#6:#3},%d0 \|get dest reg no 151 \| If the exception bit set is E3, the exceptional operand from the 154 btstb #E3,E_BYTE(%a6) 232 \| ;double $3ff $3fe`
D	gen_except.S	`80 bfextu CMDREG1B(%a6){#10:#3},%d1 \|extract bit 3,4,5 168 \| exception is to set the E1/E3 byte and clr the U flag. 170 \| operr, and dz. commonE3 does this for E3 exceptions, which 182 bsetb #E3,E_BYTE(%a6) \|set E3 flag 190 bsetb #E3,E_BYTE(%a6) \|set E3 flag 199 bfextu CMDREG1B(%a6){#10:#3},%d1 \|extract bit 3,4,5 300 bsetb #E3,E_BYTE(%a6) \|set E3 flag 311 bfextu CMDREG1B(%a6){#10:#3},%d1 \|extract bit 3,4,5 319 \| NOTE * Bug fix for errata (0d43b #3)`
D	util.S	`103 btstb #E3,E_BYTE(%a6) \|check for nu exception 159 \| This entry point used by x_ovfl. (opclass 3 only) 182 lsll #2,%d0 \|move round precision to d0{3:2} 184 orl %d1,%d0 \|index is fmt:mode in d0{3:0} 328 \| if E3 355 btstb #E3,E_BYTE(%a6) 423 btstb #E3,E_BYTE(%a6) 426 clrl %d0 \|if E3, only opclass 0x0 is possible 430 bfextu %d0{#0:#3},%d0 \|shift opclass bits d0{31:29} to d0{2:0} 436 \| If E3, the format is extended. [all …]`
/kernel/linux/linux-5.10/drivers/edac/
D	ie31200_edac.c	3 * Intel E3-1200 6 * Support for the E3-1200 processor family. Heavily based on previous 14 * 0108: Xeon E3-1200 Processor Family DRAM Controller 15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller 16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller 18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller 20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller 21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers [all …]
/kernel/liteos_a/testsuites/unittest/libc/time/clock/full/
D	clock_test_010.cpp	`15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 76 (void)SleepTest(3); // 3, ns. in ClockTestThread() 77 (void)SleepTest(40e3); // 40us in ClockTestThread() 78 (void)SleepTest(50e3); // 50us in ClockTestThread() 79 (void)SleepTest(50e3 + 1); // 50us+1ns in ClockTestThread() 80 (void)SleepTest(60e3); // 60us in ClockTestThread() 81 (void)SleepTest(65e3); // 65us in ClockTestThread()`
/kernel/linux/linux-6.6/Documentation/input/
D	shape.svg	9 …<polyline transform="translate(-121.88 -68.4)" points="3600 3600 3e3 3600" fill="none" stroke="#00… 10 …<polyline transform="translate(-121.88 -68.4)" points="4125 3075 3e3 3075" fill="none" stroke="#00… 17 …<polyline transform="translate(-121.88 -68.4)" points="3e3 3167 3e3 3583" fill="none" stroke="#000… 18 …<polyline transform="translate(-121.88 -68.4)" points="2970 3478 3e3 3598 3030 3478" fill="none" s… 19 …<polyline transform="translate(-121.88 -68.4)" points="3030 3272 3e3 3152 2970 3272" fill="none" s…
D	interactive.svg	`2 …<polyline transform="translate(-18.5,-16.294)" points="1200 3600 1800 3600 2400 4800 3e3 4800 4200… 6 …<polyline transform="translate(-18.5,-16.294)" points="3e3 4800 3e3 6525 3600 7125 3600 7800" fill…`
/kernel/linux/linux-5.10/Documentation/input/
D	shape.svg	9 …<polyline transform="translate(-121.88 -68.4)" points="3600 3600 3e3 3600" fill="none" stroke="#00… 10 …<polyline transform="translate(-121.88 -68.4)" points="4125 3075 3e3 3075" fill="none" stroke="#00… 17 …<polyline transform="translate(-121.88 -68.4)" points="3e3 3167 3e3 3583" fill="none" stroke="#000… 18 …<polyline transform="translate(-121.88 -68.4)" points="2970 3478 3e3 3598 3030 3478" fill="none" s… 19 …<polyline transform="translate(-121.88 -68.4)" points="3030 3272 3e3 3152 2970 3272" fill="none" s…
D	interactive.svg	`2 …<polyline transform="translate(-18.5,-16.294)" points="1200 3600 1800 3600 2400 4800 3e3 4800 4200… 6 …<polyline transform="translate(-18.5,-16.294)" points="3e3 4800 3e3 6525 3600 7125 3600 7800" fill…`
/kernel/linux/linux-6.6/arch/arm/crypto/
D	ghash-ce-core.S	`122 vext.8 t2l, \ad, \ad, #3 @ A3 126 vext.8 t4l, \bd, \bd, #3 @ B3 206 b 3f 211 tst r0, #3 // skip until #blocks is a 304 3: /* multiply XL by SHASH in GF(2^128) */ 356 vext.8 s3l, SHASH_L, SHASH_L, #3 360 vext.8 s3h, SHASH_H, SHASH_H, #3 376 e3 .req q12 467 vmov e3, ctr 470 aes_encrypt ip, r6, e0, e1, e2, e3 [all …]`
/kernel/linux/linux-6.6/drivers/gpu/drm/renesas/rcar-du/
D	rcar_lvds_regs.h	`26 #define LVDCR1_CHSTBY(n) (3 << (2 + (n) * 2)) 27 #define LVDCR1_CLKSTBY (3 << 0) 39 /* Gen3 but V3M,D3 and E3 / 45 / D3 and E3 / 51 #define LVDPLLCR_CKSEL_EXTAL (3 << 17) 58 #define LVDPLLCR_PLLN(n) ((n) << 3) 69 #define LVDCTRCR_CTR2SEL_HSYNC (3 << 8) 75 #define LVDCTRCR_CTR1SEL_CDE (3 << 4) 81 #define LVDCTRCR_CTR0SEL_ODD (3 << 0) 86 #define LVDCHCR_CHSEL_CH(n, c) ((((c) - (n)) & 3) << ((n) 4)) [all …]`
/kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/
D	rcar_lvds_regs.h	`26 #define LVDCR1_CHSTBY(n) (3 << (2 + (n) * 2)) 27 #define LVDCR1_CLKSTBY (3 << 0) 39 /* Gen3 but V3M,D3 and E3 / 45 / D3 and E3 / 51 #define LVDPLLCR_CKSEL_EXTAL (3 << 17) 58 #define LVDPLLCR_PLLN(n) ((n) << 3) 69 #define LVDCTRCR_CTR2SEL_HSYNC (3 << 8) 75 #define LVDCTRCR_CTR1SEL_CDE (3 << 4) 81 #define LVDCTRCR_CTR0SEL_ODD (3 << 0) 86 #define LVDCHCR_CHSEL_CH(n, c) ((((c) - (n)) & 3) << ((n) 4)) [all …]`
/kernel/linux/linux-5.10/drivers/soc/renesas/
D	r8a77990-sysc.c	`3 * Renesas R-Car E3 System Controller 27 { "3dg-a", 0x100, 0, R8A77990_PD_3DG_A, R8A77990_PD_ALWAYS_ON }, 28 { "3dg-b", 0x100, 1, R8A77990_PD_3DG_B, R8A77990_PD_3DG_A }, 31 /* Fixups for R-Car E3 ES1.0 revision / 40 / Fix incorrect 3DG hierarchy */ in r8a77990_sysc_init()`
/kernel/linux/linux-6.6/drivers/pmdomain/renesas/
D	r8a77990-sysc.c	`3 * Renesas R-Car E3 System Controller 27 { "3dg-a", 0x100, 0, R8A77990_PD_3DG_A, R8A77990_PD_ALWAYS_ON }, 28 { "3dg-b", 0x100, 1, R8A77990_PD_3DG_B, R8A77990_PD_3DG_A }, 31 /* Fixups for R-Car E3 ES1.0 revision / 40 / Fix incorrect 3DG hierarchy */ in r8a77990_sysc_init()`
/kernel/linux/linux-6.6/fs/ntfs3/
D	bitmap.c	365 struct e_node e, e3; in wnd_remove_free_ext() local 395 e3 = rb_entry(n3, struct e_node, start.node); in wnd_remove_free_ext() 396 if (e3->start.key >= end_in) in wnd_remove_free_ext() 399 if (e3->count.key == wnd->extent_max) in wnd_remove_free_ext() 402 end3 = e3->start.key + e3->count.key; in wnd_remove_free_ext() 404 e3->start.key = end_in; in wnd_remove_free_ext() 405 rb_erase(&e3->count.node, &wnd->count_tree); in wnd_remove_free_ext() 406 e3->count.key = end3 - end_in; in wnd_remove_free_ext() 407 rb_insert_count(&wnd->count_tree, e3); in wnd_remove_free_ext() 412 rb_erase(&e3->start.node, &wnd->start_tree); in wnd_remove_free_ext() [all …]
/kernel/linux/linux-5.10/lib/
D	locking-selftest.c	`275 static void name##_123(void) { E1(); E2(); E3(); } \ 276 static void name##_132(void) { E1(); E3(); E2(); } \ 277 static void name##_213(void) { E2(); E1(); E3(); } \ 278 static void name##_231(void) { E2(); E3(); E1(); } \ 279 static void name##_312(void) { E3(); E1(); E2(); } \ 280 static void name##_321(void) { E3(); E2(); E1(); } 896 #define E3() \ macro 926 #undef E3 945 #define E3() \ macro 974 #undef E3 [all …]`
/kernel/linux/linux-6.6/Documentation/admin-guide/hw-vuln/
D	processor_mmio_stale_data.rst	37 Intel Xeon server E3) uncore implementation. The sideband response buffer is 47 Intel Xeon server E3) uncore implementation. Similar to the sideband response 68 the fill buffer. It is limited to the client (including Intel Xeon server E3) 75 the client (including Intel Xeon server E3) uncore implementation. 80 processors for the server market (excluding Intel Xeon E3 processors) are 89 SKYLAKE_L 06_4EH 3 91 SKYLAKE_X 06_55H 3,4,6,7,11 92 BROADWELL_D 06_56H 3,4,5 93 SKYLAKE 06_5EH 3 103 COMETLAKE 06_A5H 2,3,5 [all …]
/kernel/linux/linux-5.10/Documentation/admin-guide/hw-vuln/
D	processor_mmio_stale_data.rst	37 Intel Xeon server E3) uncore implementation. The sideband response buffer is 47 Intel Xeon server E3) uncore implementation. Similar to the sideband response 68 the fill buffer. It is limited to the client (including Intel Xeon server E3) 75 the client (including Intel Xeon server E3) uncore implementation. 80 processors for the server market (excluding Intel Xeon E3 processors) are 89 SKYLAKE_L 06_4EH 3 91 SKYLAKE_X 06_55H 3,4,6,7,11 92 BROADWELL_D 06_56H 3,4,5 93 SKYLAKE 06_5EH 3 103 COMETLAKE 06_A5H 2,3,5 [all …]

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