| /kernel/linux/linux-6.6/Documentation/userspace-api/media/v4l/ |
| D | metafmt-vsp1-hgo.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
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| D | metafmt-vsp1-hgt.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgt:
9 Renesas R-Car VSP1 2-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1
16 2-D Histogram (HGT) engine.
28 The Saturation position **n** (0 - 31) of the bucket in the matrix is
33 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
43 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5
50 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L
72 0L <= 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U
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| /kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/ |
| D | pixfmt-meta-vsp1-hgo.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
[all …]
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| D | pixfmt-meta-vsp1-hgt.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgt:
9 Renesas R-Car VSP1 2-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1
16 2-D Histogram (HGT) engine.
28 The Saturation position **n** (0 - 31) of the bucket in the matrix is
33 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
43 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5
50 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L
72 0L <= 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U
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| /kernel/linux/linux-5.10/drivers/net/dsa/sja1105/ |
| D | sja1105_ethtool.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 #define SJA1105_SIZE_MAC_AREA (0x02 * 4)
7 #define SJA1105_SIZE_HL1_AREA (0x10 * 4)
8 #define SJA1105_SIZE_HL2_AREA (0x4 * 4)
9 #define SJA1105_SIZE_QLEVEL_AREA (0x8 * 4) /* 0x4 to 0xB */
10 #define SJA1105_SIZE_ETHER_AREA (0x17 * 4)
104 /* Make pointer arithmetic work on 4 bytes */ in sja1105_port_status_mac_unpack()
107 sja1105_unpack(p + 0x0, &status->n_runt, 31, 24, 4); in sja1105_port_status_mac_unpack()
108 sja1105_unpack(p + 0x0, &status->n_soferr, 23, 16, 4); in sja1105_port_status_mac_unpack()
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| /kernel/linux/linux-5.10/arch/powerpc/xmon/ |
| D | ppc-opc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
173 /* The BD field in a B form instruction when the - modifier is used.
179 /* The BD field in a B form instruction when the - modifier is used
224 /* The BO field in a B form instruction when the + or - modifier is
254 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
411 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
412 { -1, -1, NULL, NULL, 0},
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| /kernel/linux/linux-6.6/arch/powerpc/xmon/ |
| D | ppc-opc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
173 /* The BD field in a B form instruction when the - modifier is used.
179 /* The BD field in a B form instruction when the - modifier is used
224 /* The BO field in a B form instruction when the + or - modifier is
254 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
411 /* If the FXM4 operand is omitted, use the sentinel value -1. */
412 { -1, -1, NULL, NULL, 0},
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| /kernel/linux/linux-6.6/arch/powerpc/crypto/ |
| D | poly1305-p10le_64.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
28 # setup r^4, r^3, r^2, r vectors
29 # vs [r^1, r^3, r^2, r^4]
56 #include <asm/asm-offsets.h>
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| D | chacha-p10le-8x.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
17 # 4. c += d; b ^= c; b <<<= 7
24 # 4 blocks (a b c d)
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
100 SAVE_GPR 31, 248, 1
114 SAVE_VRS 31, 176, 9
133 SAVE_VSX 31, 464, 9
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| /kernel/linux/linux-6.6/arch/alpha/include/asm/ |
| D | xor.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
53 .align 4 \n\
60 ldq $4,16($17) \n\
78 xor $4,$5,$4 \n\
82 stq $4,16($17) \n\
108 .align 4 \n\
115 ldq $4,8($18) \n\
131 xor $3,$4,$4 # 6 cycles from $4 load \n\
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| /kernel/linux/linux-5.10/arch/alpha/include/asm/ |
| D | xor.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
34 .align 4 \n\
41 ldq $4,16($17) \n\
59 xor $4,$5,$4 \n\
63 stq $4,16($17) \n\
89 .align 4 \n\
96 ldq $4,8($18) \n\
112 xor $3,$4,$4 # 6 cycles from $4 load \n\
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| /kernel/linux/linux-5.10/drivers/infiniband/hw/i40iw/ |
| D | i40iw_register.h | 3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
45 #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31
54 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
62 #define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /*…
63 #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CO…
68 #define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4
86 #define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4
90 #define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
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| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| D | clk-mt2712-apmixedsys.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "clk-pll.h"
13 #include "clk-mtk.h"
15 #include <dt-bindings/clock/mt2712-clk.h>
57 { .div = 4, .freq = 157625000 },
66 { .div = 4, .freq = 157625000 },
75 { .div = 4, .freq = 125125000 },
81 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
83 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
85 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
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| /kernel/linux/linux-5.10/drivers/infiniband/hw/hns/ |
| D | hns_roce_hw_v2.h | 2 * Copyright (c) 2016-2017 Hisilicon Limited.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
88 #define HNS_ROCE_V2_IDX_ENTRY_SZ 4
129 #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4
293 #define V2_CQC_BYTE_4_OVER_IGNORE_S 4
310 #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
322 #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
331 #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
345 #define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
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| /kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7603/ |
| D | regs.h | 1 /* SPDX-License-Identifier: ISC */
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
51 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
64 #define MT_TXTIME_THRESH(n) (MT_TXTIME_THRESH_BASE + ((n) * 4))
67 #define MT_PAGE_COUNT(n) (MT_PAGE_COUNT_BASE + ((n) * 4))
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/ |
| D | regs.h | 1 /* SPDX-License-Identifier: ISC */
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
44 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
51 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
64 #define MT_TXTIME_THRESH(n) (MT_TXTIME_THRESH_BASE + ((n) * 4))
67 #define MT_PAGE_COUNT(n) (MT_PAGE_COUNT_BASE + ((n) * 4))
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| /kernel/linux/linux-6.6/arch/alpha/lib/ |
| D | memset.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
41 ldq_u $31,0($30) /* .. E1 */
51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
53 beq $3,aligned /* .. E1 (note EV5 zero-latency forwarding) */
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| D | clear_user.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * We have to make sure that $0 is always up-to-date and contains the
19 .long 99b - .; \
20 lda $31, $exception-99b($31); \
25 .align 4
33 and $1, 3, $4 # e0 :
34 beq $4, 1f # .. e1 :
36 0: EX( stq_u $31, 0($16) ) # e0 : zero one word
38 subq $4, 1, $4 # e0 :
40 bne $4, 0b # e1 :
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| /kernel/linux/linux-5.10/arch/alpha/lib/ |
| D | memset.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * This routine is "moral-ware": you are free to use it any way you wish, and
35 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
36 sll $17,16,$1 /* E1 (p-c latency, next cycle) */
38 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
39 sll $17,32,$1 /* E1 (p-c latency, next cycle) */
40 bis $17,$1,$17 /* E0 (p-c latency, next cycle) */
41 ldq_u $31,0($30) /* .. E1 */
51 beq $1,within_one_quad /* .. E1 (note EV5 zero-latency forwarding) */
53 beq $3,aligned /* .. E1 (note EV5 zero-latency forwarding) */
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| D | clear_user.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * We have to make sure that $0 is always up-to-date and contains the
19 .long 99b - .; \
20 lda $31, $exception-99b($31); \
25 .align 4
33 and $1, 3, $4 # e0 :
34 beq $4, 1f # .. e1 :
36 0: EX( stq_u $31, 0($16) ) # e0 : zero one word
38 subq $4, 1, $4 # e0 :
40 bne $4, 0b # e1 :
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| /kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/ |
| D | mt76_connac3_mac.h | 1 /* SPDX-License-Identifier: ISC */
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
34 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
53 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
71 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
83 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
97 #define MT_RXD10_QOS_CTL GENMASK(31, 16)
99 #define MT_RXD11_HT_CONTROL GENMASK(31, 0)
101 /* P-RXV */
103 #define MT_PRXV_TX_DCM BIT(4)
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/ |
| D | mac.h | 1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
34 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
42 #define MT_RXD1_NORMAL_BEACON_MC BIT(4)
50 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
70 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
81 #define MT_RXV1_ACID_DET_H BIT(31)
97 #define MT_RXV2_SEL_ANT BIT(31)
103 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
106 #define MT_RXV4_RCPI3 GENMASK(31, 24)
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| /kernel/linux/linux-5.10/drivers/clk/sunxi-ng/ |
| D | ccu-sun9i-a80.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
26 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 .enable = BIT(31),
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
50 .enable = BIT(31),
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
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| /kernel/linux/linux-6.6/drivers/clk/sunxi-ng/ |
| D | ccu-sun9i-a80.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
26 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 .enable = BIT(31),
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
50 .enable = BIT(31),
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
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| /kernel/linux/linux-6.6/arch/arm64/tools/ |
| D | sysreg | 1 # SPDX-License-Identifier: GPL-2.0-only
44 # NI - Not implemented
45 # IMP - Implemented
53 Field 31:0 DTRRX
57 Res0 63:31
69 Field 31 TFO
93 Field 31:0 DTRTX
98 Field 31:0 EDECCR
101 Sysreg OSLAR_EL1 2 0 1 0 4
108 UnsignedEnum 31:28 RAS
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