Searched +full:4 +full:- +full:bit (Results 1 – 25 of 1179) sorted by relevance
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1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */3 * Copyright (C) 2015-2017 Dialog Semiconductor151 * Bit fields158 #define DA9062AA_WRITE_MODE_MASK BIT(6)160 #define DA9062AA_REVERT_MASK BIT(7)166 #define DA9062AA_DVC_BUSY_MASK BIT(2)172 #define DA9062AA_GPI1_MASK BIT(1)174 #define DA9062AA_GPI2_MASK BIT(2)176 #define DA9062AA_GPI3_MASK BIT(3)177 #define DA9062AA_GPI4_SHIFT 4[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */3 * Copyright (C) ST-Ericsson SA 201083 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */9 * Author: yanglsh@embest-tech.com32 /* LDO for Low-Power State Retention */236 #define BD71815_BUCK_PWM_FIXED BIT(4)237 #define BD71815_BUCK_SNVS_ON BIT(3)238 #define BD71815_BUCK_RUN_ON BIT(2)239 #define BD71815_BUCK_LPSR_ON BIT(1)240 #define BD71815_BUCK_SUSP_ON BIT(0)243 #define BD71815_BUCK_DVSSEL BIT(7)244 #define BD71815_BUCK_STBY_DVS BIT(6)[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/89 #define TPS65219_REG_INT_SYS_POS 4103 #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6)104 #define TPS65219_BUCKS_BW_SEL_MASK BIT(7)106 #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT)107 #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7)109 #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0)110 #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1)111 #define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2)[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/97 #define LP87565_BUCK_CTRL_1_EN BIT(7)98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)119 #define LP87565_RESET_SW_RESET BIT(0)121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)[all …]
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */2 /* Copyright 2013-2015 Freescale Semiconductor Inc.16 * DPKG_NUM_OF_MASKS - Number of masks per key extraction18 #define DPKG_NUM_OF_MASKS 421 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile26 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types38 * enum dpkg_extract_type - Enumeration for selecting extraction type41 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;52 * struct dpkg_mask - A structure for defining a single extraction mask64 #define NH_FLD_ETH_DA BIT(0)[all …]
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */2 /* Copyright 2013-2015 Freescale Semiconductor Inc.18 #define DPKG_NUM_OF_MASKS 425 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types37 * enum dpkg_extract_type - Enumeration for selecting extraction type40 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;51 * struct dpkg_mask - A structure for defining a single extraction mask63 #define NH_FLD_ETH_DA BIT(0)64 #define NH_FLD_ETH_SA BIT(1)65 #define NH_FLD_ETH_LENGTH BIT(2)[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */2 /* Copyright (c) 2018-2023, Intel Corporation. */4 /* Machine-generated file */9 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))10 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4))19 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)20 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)21 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)22 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)30 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */24 #define SW_CHIP_ID_S 434 #define SW_NEW_BACKOFF BIT(7)35 #define SW_GLOBAL_RESET BIT(6)36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)38 #define SW_LINK_AUTO_AGING BIT(0)42 #define SW_HUGE_PACKET BIT(6)43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */5 * Copyright (C) 2017-2018 Microchip Technology Inc.12 #define KS_PRIO_S 414 /* 0 - Operation */39 #define SWITCH_REVISION_S 444 #define PME_ENABLE BIT(1)45 #define PME_POLARITY BIT(0)49 #define SW_GIGABIT_ABLE BIT(6)50 #define SW_REDUNDANCY_ABLE BIT(5)51 #define SW_AVB_ABLE BIT(4)[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */29 #define TSI148_MAX_MAILBOX 4 /* Max Mail Box registers */37 void (*lm_callback[4])(void *); /* Called in interrupt handler */38 void *lm_data[4];50 * Layout of a DMAC Linked-List Descriptor53 * correctly laid out - It must also be aligned on 64-bit boundaries.70 * The descriptor needs to be aligned on a 64-bit boundary, we increase79 * TSI148 ASIC register structure overlays and bit field definitions.83 * PCFS - PCI Configuration Space Registers84 * LCSR - Local Control and Status Registers[all …]
1 // SPDX-License-Identifier: GPL-2.07 #include "phy-mtk-io.h"8 #include "phy-mtk-mipi-dsi.h"11 #define RG_DSI_LDOCORE_EN BIT(0)12 #define RG_DSI_CKG_LDOOUT_EN BIT(1)14 #define RG_DSI_LD_IDX_SEL GENMASK(6, 4)16 #define RG_DSI_DSICLK_FREQ_SEL BIT(10)17 #define RG_DSI_LPTX_CLMP_EN BIT(11)24 #define RG_DSI_LNTx_LDOOUT_EN BIT(0)25 #define RG_DSI_LNTx_CKLANE_EN BIT(1)[all …]
1 /* SPDX-License-Identifier: GPL-2.0+ */3 * Copyright 2016-2017 Google, Inc5 * Fairchild FUSB302 Type-C Chip Driver13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)[all …]
1 // SPDX-License-Identifier: GPL-2.010 #define RG_DSI_LDOCORE_EN BIT(0)11 #define RG_DSI_CKG_LDOOUT_EN BIT(1)13 #define RG_DSI_LD_IDX_SEL (7 << 4)15 #define RG_DSI_DSICLK_FREQ_SEL BIT(10)16 #define RG_DSI_LPTX_CLMP_EN BIT(11)23 #define RG_DSI_LNTx_LDOOUT_EN BIT(0)24 #define RG_DSI_LNTx_CKLANE_EN BIT(1)25 #define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2)26 #define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3)[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */3 * DA9150 MFD Driver - Registers160 #define DA9150_WRITE_MODE_MASK BIT(6)162 #define DA9150_REVERT_MASK BIT(7)172 #define DA9150_VFAULT_STAT_MASK BIT(0)174 #define DA9150_TFAULT_STAT_MASK BIT(1)178 #define DA9150_VDD33_STAT_MASK BIT(0)180 #define DA9150_VDD33_SLEEP_MASK BIT(1)182 #define DA9150_LFOSC_STAT_MASK BIT(7)186 #define DA9150_GPIOA_STAT_MASK BIT(0)[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */2 /* Copyright(c) 2009-2013 Realtek Corporation.*/8 /* Check document WM-20110607-Paul-RTL8188EE_Power_Architecture-R02.vsd10 * 0: POFF--Power Off11 * 1: PDN--Power Down12 * 2: CARDEMU--Card Emulation13 * 3: ACT--Active Mode14 * 4: LPS--Low Power State15 * 5: SUS--Suspend46 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \[all …]