Home
last modified time | relevance | path

Searched +full:4 +full:- +full:bits (Results 1 – 25 of 1260) sorted by relevance

12345678910>>...51

/kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/
Dpixfmt-srggb10-ipu3.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-pix-fmt-ipu3-sbggr10:
4 .. _v4l2-pix-fmt-ipu3-sgbrg10:
5 .. _v4l2-pix-fmt-ipu3-sgrbg10:
6 .. _v4l2-pix-fmt-ipu3-srggb10:
12 10-bit Bayer formats
18 sRGB / Bayer formats with 10 bits per sample with every 25 pixels packed
19 to 32 bytes leaving 6 most significant bits padding in the last byte.
22 In other respects this format is similar to :ref:`V4L2-PIX-FMT-SRGGB10`.
30 .. flat-table::
[all …]
Dpixfmt-srggb14p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB14P:
4 .. _v4l2-pix-fmt-sbggr14p:
5 .. _v4l2-pix-fmt-sgbrg14p:
6 .. _v4l2-pix-fmt-sgrbg14p:
17 14-bit packed Bayer formats
24 bits per colour. Every four consecutive samples are packed into seven
25 bytes. Each of the first four bytes contain the eight high order bits
27 significants bits of each pixel, in the same order.
29 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
[all …]
/kernel/linux/linux-6.6/drivers/crypto/hisilicon/sec2/
Dsec_crypto.h1 /* SPDX-License-Identifier: GPL-2.0 */
88 * mac_len: 0~4 bits
89 * a_key_len: 5~10 bits
90 * a_alg: 11~16 bits
95 * c_icv_len: 0~5 bits
96 * c_width: 6~8 bits
97 * c_key_len: 9~11 bits
98 * c_mode: 12~15 bits
102 /* c_alg: 0~3 bits */
107 * a_len: 0~23 bits
[all …]
/kernel/linux/linux-6.6/Documentation/userspace-api/media/v4l/
Dpixfmt-srggb10-ipu3.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-pix-fmt-ipu3-sbggr10:
4 .. _v4l2-pix-fmt-ipu3-sgbrg10:
5 .. _v4l2-pix-fmt-ipu3-sgrbg10:
6 .. _v4l2-pix-fmt-ipu3-srggb10:
13 10-bit Bayer formats
20 sRGB / Bayer formats with 10 bits per sample with every 25 pixels packed
21 to 32 bytes leaving 6 most significant bits padding in the last byte.
24 In other respects this format is similar to :ref:`V4L2-PIX-FMT-SRGGB10`.
36 .. flat-table::
[all …]
Dpixfmt-srggb14p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB14P:
4 .. _v4l2-pix-fmt-sbggr14p:
5 .. _v4l2-pix-fmt-sgbrg14p:
6 .. _v4l2-pix-fmt-sgrbg14p:
17 14-bit packed Bayer formats
24 bits per colour. Every four consecutive samples are packed into seven
25 bytes. Each of the first four bytes contain the eight high order bits
27 significants bits of each pixel, in the same order.
29 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
[all …]
Dpixfmt-packed-yuv.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-yuv:
15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
18 denotes bits of the alpha component (if supported by the format), and 'X'
19 denotes padding bits.
22 4:4:4 Subsampling
28 The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
30 seen in a 16-bit word, which is then stored in memory in little endian byte
31 order, and on the number of bits for each component. For instance the YUV565
[all …]
/kernel/linux/linux-5.10/include/rdma/
Dib_smi.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
71 u8 linkspeed_portstate; /* 4 bits, 4 bits */
72 u8 portphysstate_linkdown; /* 4 bits, 4 bits */
73 u8 mkeyprot_resv_lmc; /* 2 bits, 3, 3 */
74 u8 linkspeedactive_enabled; /* 4 bits, 4 bits */
75 u8 neighbormtu_mastersmsl; /* 4 bits, 4 bits */
76 u8 vlcap_inittype; /* 4 bits, 4 bits */
80 u8 inittypereply_mtucap; /* 4 bits, 4 bits */
81 u8 vlstallcnt_hoqlife; /* 3 bits, 5 bits */
82 u8 operationalvl_pei_peo_fpi_fpo; /* 4 bits, 1, 1, 1, 1 */
[all …]
Dopa_port_info.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright (c) 2014-2020 Intel Corporation. All rights reserved.
12 #define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */
17 #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
23 #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
24 #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
31 #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4
61 /* 34 -reserved */
[all …]
/kernel/linux/linux-6.6/include/rdma/
Dib_smi.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
71 u8 linkspeed_portstate; /* 4 bits, 4 bits */
72 u8 portphysstate_linkdown; /* 4 bits, 4 bits */
73 u8 mkeyprot_resv_lmc; /* 2 bits, 3, 3 */
74 u8 linkspeedactive_enabled; /* 4 bits, 4 bits */
75 u8 neighbormtu_mastersmsl; /* 4 bits, 4 bits */
76 u8 vlcap_inittype; /* 4 bits, 4 bits */
80 u8 inittypereply_mtucap; /* 4 bits, 4 bits */
81 u8 vlstallcnt_hoqlife; /* 3 bits, 5 bits */
82 u8 operationalvl_pei_peo_fpi_fpo; /* 4 bits, 1, 1, 1, 1 */
[all …]
Dopa_port_info.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright (c) 2014-2020 Intel Corporation. All rights reserved.
12 #define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */
17 #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
23 #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
24 #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
31 #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4
61 /* 34 -reserved */
[all …]
/kernel/linux/linux-5.10/drivers/pci/
Dpci-bridge-emul.c1 // SPDX-License-Identifier: GPL-2.0
21 #include "pci-bridge-emul.h"
29 * struct pci_bridge_reg_behavior - register bits behaviors
30 * @ro: Read-Only bits
31 * @rw: Read-Write bits
32 * @w1c: Write-1-to-Clear bits
34 * Reads and Writes will be filtered by specified behavior. All other bits not
37 * multi-bit fields) when read".
40 /* Read-only bits */
43 /* Read-write bits */
[all …]
/kernel/linux/linux-6.6/drivers/pci/
Dpci-bridge-emul.c1 // SPDX-License-Identifier: GPL-2.0
21 #include "pci-bridge-emul.h"
28 * struct pci_bridge_reg_behavior - register bits behaviors
29 * @ro: Read-Only bits
30 * @rw: Read-Write bits
31 * @w1c: Write-1-to-Clear bits
33 * Reads and Writes will be filtered by specified behavior. All other bits not
36 * multi-bit fields) when read".
39 /* Read-only bits */
42 /* Read-write bits */
[all …]
/kernel/linux/linux-5.10/tools/edid/
Dedid.S18 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
36 /* Provide defaults for the timing bits */
48 ((((v1-'@')&0x1f)<<10)+(((v2-'@')&0x1f)<<5)+((v3-'@')&0x1f))
50 #define lsbs2(v1,v2) (((v1&0x0f)<<4)+(v2&0x0f))
51 #define msbs2(v1,v2) ((((v1>>8)&0x0f)<<4)+((v2>>8)&0x0f))
53 ((((v1>>8)&0x03)<<6)+(((v2>>8)&0x03)<<4)+\
54 (((v3>>4)&0x03)<<2)+((v4>>4)&0x03))
68 /* Serial number. 32 bits, little endian. */
74 /* Year of manufacture, less 1990. (1990-2245)
76 year: .byte YEAR-1990
[all …]
/kernel/linux/linux-6.6/tools/edid/
Dedid.S18 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
36 /* Provide defaults for the timing bits */
48 ((((v1-'@')&0x1f)<<10)+(((v2-'@')&0x1f)<<5)+((v3-'@')&0x1f))
50 #define lsbs2(v1,v2) (((v1&0x0f)<<4)+(v2&0x0f))
51 #define msbs2(v1,v2) ((((v1>>8)&0x0f)<<4)+((v2>>8)&0x0f))
53 ((((v1>>8)&0x03)<<6)+(((v2>>8)&0x03)<<4)+\
54 (((v3>>4)&0x03)<<2)+((v4>>4)&0x03))
68 /* Serial number. 32 bits, little endian. */
74 /* Year of manufacture, less 1990. (1990-2245)
76 year: .byte YEAR-1990
[all …]
/kernel/linux/linux-5.10/drivers/crypto/hisilicon/sec2/
Dsec_crypto.h1 /* SPDX-License-Identifier: GPL-2.0 */
69 * mac_len: 0~4 bits
70 * a_key_len: 5~10 bits
71 * a_alg: 11~16 bits
76 * c_icv_len: 0~5 bits
77 * c_width: 6~8 bits
78 * c_key_len: 9~11 bits
79 * c_mode: 12~15 bits
83 /* c_alg: 0~3 bits */
88 * a_len: 0~23 bits
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
Doaktrail.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2007-2011, Intel Corporation.
16 u8 hblank_hi:4;
17 u8 hactive_hi:4;
20 u8 vblank_hi:4;
21 u8 vactive_hi:4;
24 u8 vsync_pulse_width_lo:4;
25 u8 vsync_offset_lo:4;
32 u8 height_mm_hi:4;
33 u8 width_mm_hi:4;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
Doaktrail.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2007-2011, Intel Corporation.
16 u8 hblank_hi:4;
17 u8 hactive_hi:4;
20 u8 vblank_hi:4;
21 u8 vactive_hi:4;
24 u8 vsync_pulse_width_lo:4;
25 u8 vsync_offset_lo:4;
32 u8 height_mm_hi:4;
33 u8 width_mm_hi:4;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/
Ddc_dp_types.h35 LANE_COUNT_FOUR = 4,
49 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
50 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
51 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
52 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
53 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane
54 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
55 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane
56 LINK_RATE_HIGH3 = 0x1E // Rate_8 (HBR3)- 8.10 Gbps/Lane
138 uint8_t MINOR:4;
[all …]
/kernel/linux/linux-5.10/include/drm/
Ddrm_dsc.h1 /* SPDX-License-Identifier: MIT
28 #define DSC_PPS_VERSION_MAJOR_SHIFT 4
29 #define DSC_PPS_BPC_SHIFT 4
35 #define DSC_PPS_CONVERT_RGB_SHIFT 4
39 #define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4
48 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
64 * Bits/group offset to apply to target for this group
70 * struct drm_dsc_config - Parameters required to configure DSC
78 * Bits per component for previous reconstructed line buffer
82 * @bits_per_component: Bits per component to code (8/10/12)
[all …]
/kernel/linux/linux-6.6/include/drm/display/
Ddrm_dsc.h1 /* SPDX-License-Identifier: MIT
28 #define DSC_PPS_VERSION_MAJOR_SHIFT 4
29 #define DSC_PPS_BPC_SHIFT 4
35 #define DSC_PPS_CONVERT_RGB_SHIFT 4
39 #define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4
48 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
64 * Bits/group offset to apply to target for this group
70 * struct drm_dsc_config - Parameters required to configure DSC
78 * Bits per component for previous reconstructed line buffer
82 * @bits_per_component: Bits per component to code (8/10/12)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/
Dsocionext,uniphier-efuse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/socionext,uniphier-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Keiji Hayashibara <hayashibara.keiji@socionext.com>
11 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
14 - $ref: nvmem.yaml#
18 const: socionext,uniphier-efuse
24 - compatible
25 - reg
[all …]
/kernel/linux/linux-6.6/include/linux/irqchip/
Dirq-bcm2836.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
13 * next 2 bits identify the CPU that the GPU FIQ goes to.
16 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
18 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
21 * The low 4 bits of this are the CPU's timer IRQ enables, and the
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
23 * bits).
27 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
[all …]
/kernel/linux/linux-5.10/include/linux/irqchip/
Dirq-bcm2836.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
13 * next 2 bits identify the CPU that the GPU FIQ goes to.
16 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
18 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
21 * The low 4 bits of this are the CPU's timer IRQ enables, and the
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
23 * bits).
27 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/
Ddc_dp_types.h36 LANE_COUNT_FOUR = 4,
50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
[all …]
/kernel/linux/linux-6.6/drivers/iio/dac/
Dad5686.c1 // SPDX-License-Identifier: GPL-2.0
33 return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1; in ad5686_get_powerdown_mode()
42 st->pwr_down_mode &= ~(0x3 << (chan->channel * 2)); in ad5686_set_powerdown_mode()
43 st->pwr_down_mode |= ((mode + 1) << (chan->channel * 2)); in ad5686_set_powerdown_mode()
60 return sysfs_emit(buf, "%d\n", !!(st->pwr_down_mask & in ad5686_read_dac_powerdown()
61 (0x3 << (chan->channel * 2)))); in ad5686_read_dac_powerdown()
81 st->pwr_down_mask |= (0x3 << (chan->channel * 2)); in ad5686_write_dac_powerdown()
83 st->pwr_down_mask &= ~(0x3 << (chan->channel * 2)); in ad5686_write_dac_powerdown()
85 switch (st->chip_info->regmap_type) { in ad5686_write_dac_powerdown()
98 if (chan->channel > 0x7) in ad5686_write_dac_powerdown()
[all …]

12345678910>>...51