| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
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| /kernel/linux/linux-6.6/Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ufs/ |
| D | tc-dwc-g210-pltfrm.txt | 3 DWC_UFS nodes are defined to describe on-chip UFS host controllers and MPHY.
7 - compatible : compatible list must contain the PHY type & version:
8 "snps,g210-tc-6.00-20bit"
9 "snps,g210-tc-6.00-40bit"
11 "snps,dwc-ufshcd-1.40a"
13 "jedec,ufs-1.1"
14 "jedec,ufs-2.0"
16 - reg : <registers mapping>
17 - interrupts : <interrupt mapping for UFS host controller IRQ>
19 Example for a setup using a 1.40a DWC Controller with a 6.00 G210 40-bit TC:
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/platforms/ |
| D | Kconfig.cputype | 1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
18 There are five families of 32 bit PowerPC chips supported.
46 config 40x
47 bool "AMCC 40x"
85 There are two families of 64 bit PowerPC chips supported.
198 bool "40x family"
199 depends on 40x
282 default "-mtune=power10" if $(cc-option,-mtune=power10)
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| /kernel/linux/linux-5.10/arch/alpha/kernel/ |
| D | sys_sable.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
55 * For SABLE, which is really baroque, we manage 40 IRQ's, but the
58 * 0-7 (char at 536)
59 * 8-15 (char at 53a)
60 * 16-23 (char at 53c)
64 * Bit Meaning Kernel IRQ
[all …]
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| D | sys_wildfire.c | 1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
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| /kernel/linux/linux-6.6/arch/alpha/kernel/ |
| D | sys_sable.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
55 * For SABLE, which is really baroque, we manage 40 IRQ's, but the
58 * 0-7 (char at 536)
59 * 8-15 (char at 53a)
60 * 16-23 (char at 53c)
64 * Bit Meaning Kernel IRQ
[all …]
|
| D | sys_wildfire.c | 1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
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| /kernel/linux/linux-6.6/tools/testing/selftests/bpf/progs/ |
| D | verifier_spill_fill.c | 1 // SPDX-License-Identifier: GPL-2.0
21 *(u64*)(r10 - 8) = r1; \ in __retval()
23 r2 = *(u64*)(r10 - 8); \ in __retval()
38 *(u64*)(r10 - 8) = r6; \ in valid_spill_fill_skb_mark()
39 r0 = *(u64*)(r10 - 8); \ in valid_spill_fill_skb_mark()
55 *(u64*)(r10 - 8) = r1; \ in spill_fill_ptr_to_mem()
65 *(u64*)(r10 - 8) = r6; \ in spill_fill_ptr_to_mem()
67 r7 = *(u64*)(r10 - 8); \ in spill_fill_ptr_to_mem()
93 *(u64*)(r10 - 8) = r1; \ in with_invalid_reg_offset_0()
129 *(u64*)(r10 - 8) = r1; \ in __flag()
[all …]
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| /kernel/linux/linux-5.10/arch/mips/loongson64/ |
| D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
9 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
10 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
18 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
19 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
|
| /kernel/linux/linux-6.6/arch/mips/loongson64/ |
| D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
9 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
10 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
18 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
19 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
|
| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/ |
| D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
43 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
44 {"TC58NVG6D2 64G 3.3V 8-bit",
46 SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
47 {"SDTNQGAMA 64G 3.3V 8-bit",
[all …]
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| /kernel/linux/linux-5.10/drivers/auxdisplay/ |
| D | panel.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu>
5 * Copyright (C) 2016-2017 Glider bvba
10 * The LCD module may either be an HD44780-like 8-bit parallel LCD, or a 1-bit
15 * data output pins or to the ground. The combinations have to be hard-coded
22 * - the initialization/deinitialization process is very dirty and should
26 * - document 24 keys keyboard (3 rows of 8 cols, 32 diodes + 2 inputs)
27 * - make the LCD a part of a virtual screen of Vx*Vy
28 * - make the inputs list smp-safe
29 * - change the keyboard to a double mapping : signals -> key_id -> values
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/intel/pxa/ |
| D | pxa3xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | pxa3xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
[all …]
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| /kernel/linux/linux-6.6/arch/x86/lib/ |
| D | csum-partial_64.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * arch/x86_64/lib/csum-partial.c
6 * in an architecture-specific manner due to speed.
12 #include <asm/word-at-a-time.h>
35 * Returns a 32bit checksum.
41 * checksums on IPv6 headers (40 bytes) and other small parts.
42 * it's best to have buff aligned on a 64-bit boundary
48 /* Do two 40-byte chunks in parallel to get better ILP */ in csum_partial()
53 temp64_2 = update_csum_40b(temp64_2, buff + 40); in csum_partial()
55 len -= 80; in csum_partial()
[all …]
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| /kernel/linux/linux-6.6/Documentation/powerpc/ |
| D | associativity.rst | 9 are represented as being members of a sub-grouping domain. This performance
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
23 ------
27 ------
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
34 The “ibm,associativity-reference-points” property contains a list of one or more numbers
43 if they belong to the same higher-level domains. For mismatch at every higher
48 -------
[all …]
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| /kernel/linux/linux-5.10/Documentation/powerpc/ |
| D | associativity.rst | 9 are represented as being members of a sub-grouping domain. This performance
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
23 ------
27 ------
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
34 The “ibm,associativity-reference-points” property contains a list of one or more numbers
43 if they belong to the same higher-level domains. For mismatch at every higher
48 -------
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-ep93xx/ |
| D | timer-ep93xx.c | 1 // SPDX-License-Identifier: GPL-2.0
17 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
18 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
19 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
20 * is free-running, and can't generate interrupts.
23 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
29 * a stable 40 bit time base.
116 evt->event_handler(evt); in ep93xx_timer_interrupt()
130 EP93XX_TIMER4_RATE, 200, 40, in ep93xx_timer_init()
132 sched_clock_register(ep93xx_read_sched_clock, 40, in ep93xx_timer_init()
|
| /kernel/linux/linux-6.6/arch/arm/mach-ep93xx/ |
| D | timer-ep93xx.c | 1 // SPDX-License-Identifier: GPL-2.0
17 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
18 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
19 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
20 * is free-running, and can't generate interrupts.
23 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
29 * a stable 40 bit time base.
116 evt->event_handler(evt); in ep93xx_timer_interrupt()
130 EP93XX_TIMER4_RATE, 200, 40, in ep93xx_timer_init()
132 sched_clock_register(ep93xx_read_sched_clock, 40, in ep93xx_timer_init()
|
| /kernel/linux/linux-5.10/arch/powerpc/include/asm/nohash/32/ |
| D | pte-40x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * At present, all PowerPC 400-class processors share a similar TLB
9 * 64-entry, fully-associative TLB which is maintained totally under
11 * hardware-managed, 4-entry, fully-associative TLB which serves as a
15 * There are several potential gotchas here. The 40x hardware TLBLO
23 * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
26 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
27 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
28 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
30 * - PRESENT *must* be in the bottom two bits because swap cache
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/include/asm/nohash/32/ |
| D | pte-40x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * At present, all PowerPC 400-class processors share a similar TLB
9 * 64-entry, fully-associative TLB which is maintained totally under
11 * hardware-managed, 4-entry, fully-associative TLB which serves as a
15 * There are several potential gotchas here. The 40x hardware TLBLO
23 * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
26 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
27 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
28 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
30 * - PRESENT *must* be in the bottom two bits because swap PTEs
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/octeon/ |
| D | cvmx.h | 7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
42 /* These macros for use when using 32 bit pointers. */
56 #include <asm/octeon/cvmx-asm.h>
57 #include <asm/octeon/cvmx-packet.h>
58 #include <asm/octeon/cvmx-sysinfo.h>
60 #include <asm/octeon/cvmx-ciu-defs.h>
61 #include <asm/octeon/cvmx-ciu3-defs.h>
62 #include <asm/octeon/cvmx-gpio-defs.h>
[all …]
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| /kernel/linux/linux-6.6/arch/mips/include/asm/octeon/ |
| D | cvmx.h | 7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
42 /* These macros for use when using 32 bit pointers. */
56 #include <asm/octeon/cvmx-asm.h>
57 #include <asm/octeon/cvmx-packet.h>
58 #include <asm/octeon/cvmx-sysinfo.h>
60 #include <asm/octeon/cvmx-ciu-defs.h>
61 #include <asm/octeon/cvmx-ciu3-defs.h>
62 #include <asm/octeon/cvmx-gpio-defs.h>
[all …]
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| /kernel/linux/linux-5.10/drivers/mtd/nand/spi/ |
| D | micron.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
21 #define MICRON_CFG_CR BIT(0)
24 * As per datasheet, die selection is done by the 6th bit of Die
51 return -ERANGE; in micron_8_ooblayout_ecc()
53 region->offset = mtd->oobsize / 2; in micron_8_ooblayout_ecc()
54 region->length = mtd->oobsize / 2; in micron_8_ooblayout_ecc()
63 return -ERANGE; in micron_8_ooblayout_free()
66 region->offset = 2; in micron_8_ooblayout_free()
67 region->length = (mtd->oobsize / 2) - 2; in micron_8_ooblayout_free()
[all …]
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