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/kernel/linux/linux-6.6/arch/arm64/crypto/
Dsm4-ce-asm.h12 sm4e b0.4s, v24.4s; \
13 sm4e b0.4s, v25.4s; \
14 sm4e b0.4s, v26.4s; \
15 sm4e b0.4s, v27.4s; \
16 sm4e b0.4s, v28.4s; \
17 sm4e b0.4s, v29.4s; \
18 sm4e b0.4s, v30.4s; \
19 sm4e b0.4s, v31.4s; \
20 rev64 b0.4s, b0.4s; \
29 sm4e b0.4s, v24.4s; \
[all …]
Dchacha-neon-core.S42 ld1 {v12.4s}, [x10]
46 add v0.4s, v0.4s, v1.4s
51 add v2.4s, v2.4s, v3.4s
53 shl v1.4s, v4.4s, #12
54 sri v1.4s, v4.4s, #20
57 add v0.4s, v0.4s, v1.4s
62 add v2.4s, v2.4s, v3.4s
64 shl v1.4s, v4.4s, #7
65 sri v1.4s, v4.4s, #25
68 ext v1.16b, v1.16b, v1.16b, #4
[all …]
Dsm4-neon-core.S41 zip1 RTMP0.4s, s0.4s, s1.4s; \
42 zip1 RTMP1.4s, s2.4s, s3.4s; \
43 zip2 RTMP2.4s, s0.4s, s1.4s; \
44 zip2 RTMP3.4s, s2.4s, s3.4s; \
51 zip1 RTMP0.4s, s0.4s, s1.4s; \
52 zip1 RTMP1.4s, s2.4s, s3.4s; \
53 zip2 RTMP2.4s, s0.4s, s1.4s; \
54 zip2 RTMP3.4s, s2.4s, s3.4s; \
55 zip1 RTMP4.4s, s4.4s, s5.4s; \
56 zip1 RTMP5.4s, s6.4s, s7.4s; \
[all …]
Dsm4-ce-cipher-core.S6 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8
7 .set .Lv\b\().4s, \b
19 ld1 {v8.4s}, [x2]
20 ld1 {v0.4s-v3.4s}, [x0], #64
22 ld1 {v4.4s-v7.4s}, [x0]
23 sm4e v8.4s, v0.4s
24 sm4e v8.4s, v1.4s
25 sm4e v8.4s, v2.4s
26 sm4e v8.4s, v3.4s
27 sm4e v8.4s, v4.4s
[all …]
Dsha2-ce-core.S3 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
32 add t1.4s, v\s0\().4s, \rc\().4s
33 sha256h dg0q, dg1q, t0.4s
34 sha256h2 dg1q, dg2q, t0.4s
37 add t0.4s, v\s0\().4s, \rc\().4s
39 sha256h dg0q, dg1q, t1.4s
40 sha256h2 dg1q, dg2q, t1.4s
45 sha256su0 v\s0\().4s, v\s1\().4s
47 sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
54 .align 4
[all …]
Dsm3-ce-core.S3 * sm3-ce-core.S - SM3 secure hash using ARMv8.2 Crypto Extensions
12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
13 .set .Lv\b\().4s, \b
45 sm3ss1 v5.4s, v8.4s, \t0\().4s, v9.4s
46 shl \t1\().4s, \t0\().4s, #1
47 sri \t1\().4s, \t0\().4s, #31
48 sm3tt1\ab v8.4s, v5.4s, v10.4s, \i
49 sm3tt2\ab v9.4s, v5.4s, \s0\().4s, \i
57 sm3partw1 \s4\().4s, \s0\().4s, \s3\().4s
68 sm3partw2 \s4\().4s, v7.4s, v6.4s
[all …]
Dsha1-ce-core.S3 * sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
36 add t1.4s, v\s0\().4s, \rc\().4s
39 sha1\op dg0q, \dg1, t0.4s
41 sha1\op dg0q, dg1s, t0.4s
45 add t0.4s, v\s0\().4s, \rc\().4s
48 sha1\op dg0q, dg2s, t1.4s
53 sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s
55 sha1su1 v\s0\().4s, v\s3\().4s
70 loadrc k0.4s, 0x5a827999, w6
71 loadrc k1.4s, 0x6ed9eba1, w6
[all …]
Dnh-neon-core.S41 ld1 {\k3\().4s}, [KEY], #16
44 add T0.4s, T3.4s, \k0\().4s
45 add T1.4s, T3.4s, \k1\().4s
46 add T2.4s, T3.4s, \k2\().4s
47 add T3.4s, T3.4s, \k3\().4s
54 umlal PASS0_SUMS.2d, T0.2s, T4.2s
55 umlal PASS1_SUMS.2d, T1.2s, T5.2s
56 umlal PASS2_SUMS.2d, T2.2s, T6.2s
57 umlal PASS3_SUMS.2d, T3.2s, T7.2s
64 * It's guaranteed that message_len % 16 == 0.
[all …]
Dsm4-ce-gcm-core.S19 .set .Lv\b\().4s, \b
112 sm4e b0.4s, v24.4s; \
114 sm4e b0.4s, v25.4s; \
116 sm4e b0.4s, v26.4s; \
118 sm4e b0.4s, v27.4s; \
120 sm4e b0.4s, v28.4s; \
122 sm4e b0.4s, v29.4s; \
124 sm4e b0.4s, v30.4s; \
126 sm4e b0.4s, v31.4s; \
128 rev64 b0.4s, b0.4s; \
[all …]
/kernel/linux/linux-5.10/arch/arm64/crypto/
Dchacha-neon-core.S42 ld1 {v12.4s}, [x10]
46 add v0.4s, v0.4s, v1.4s
51 add v2.4s, v2.4s, v3.4s
53 shl v1.4s, v4.4s, #12
54 sri v1.4s, v4.4s, #20
57 add v0.4s, v0.4s, v1.4s
62 add v2.4s, v2.4s, v3.4s
64 shl v1.4s, v4.4s, #7
65 sri v1.4s, v4.4s, #25
68 ext v1.16b, v1.16b, v1.16b, #4
[all …]
Dsm4-ce-core.S6 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8
7 .set .Lv\b\().4s, \b
19 ld1 {v8.4s}, [x2]
20 ld1 {v0.4s-v3.4s}, [x0], #64
22 ld1 {v4.4s-v7.4s}, [x0]
23 sm4e v8.4s, v0.4s
24 sm4e v8.4s, v1.4s
25 sm4e v8.4s, v2.4s
26 sm4e v8.4s, v3.4s
27 sm4e v8.4s, v4.4s
[all …]
Dsha2-ce-core.S3 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
32 add t1.4s, v\s0\().4s, \rc\().4s
33 sha256h dg0q, dg1q, t0.4s
34 sha256h2 dg1q, dg2q, t0.4s
37 add t0.4s, v\s0\().4s, \rc\().4s
39 sha256h dg0q, dg1q, t1.4s
40 sha256h2 dg1q, dg2q, t1.4s
45 sha256su0 v\s0\().4s, v\s1\().4s
47 sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
54 .align 4
[all …]
Dsha256-core.S_shipped40 // (**) The result is a trade-off: it's possible to improve it by
42 // on Cortex-A53 (or by 4 cycles per round).
95 sub sp,sp,#4*4
98 ldp w22,w23,[x0,#2*4]
99 ldp w24,w25,[x0,#4*4]
101 ldp w26,w27,[x0,#6*4]
106 ldp w3,w4,[x1],#2*4
107 ldr w19,[x30],#4 // *K++
131 ldr w28,[x30],#4 // *K++, w19 in next round
136 ldp w5,w6,[x1],#2*4
[all …]
Dsm3-ce-core.S3 * sm3-ce-core.S - SM3 secure hash using ARMv8.2 Crypto Extensions
11 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
12 .set .Lv\b\().4s, \b
44 sm3ss1 v5.4s, v8.4s, \t0\().4s, v9.4s
45 shl \t1\().4s, \t0\().4s, #1
46 sri \t1\().4s, \t0\().4s, #31
47 sm3tt1\ab v8.4s, v5.4s, v10.4s, \i
48 sm3tt2\ab v9.4s, v5.4s, \s0\().4s, \i
56 sm3partw1 \s4\().4s, \s0\().4s, \s3\().4s
67 sm3partw2 \s4\().4s, v7.4s, v6.4s
[all …]
Dsha1-ce-core.S3 * sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
36 add t1.4s, v\s0\().4s, \rc\().4s
39 sha1\op dg0q, \dg1, t0.4s
41 sha1\op dg0q, dg1s, t0.4s
45 add t0.4s, v\s0\().4s, \rc\().4s
48 sha1\op dg0q, dg2s, t1.4s
53 sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s
55 sha1su1 v\s0\().4s, v\s3\().4s
70 loadrc k0.4s, 0x5a827999, w6
71 loadrc k1.4s, 0x6ed9eba1, w6
[all …]
Dpoly1305-core.S_shipped36 and x9,x9,#-4
137 and x10,x14,#-4 // final reduction
193 tst x14,#-4 // see if it's carried/borrowed
239 and x10,x14,#-4 // final reduction
250 .align 4
266 str w13,[x0,#16*4] // s2
339 .align 4
389 sub x0,x0,#4
393 sub x0,x0,#4
396 bl poly1305_mult // r^4
[all …]
Dnh-neon-core.S40 ld1 {\k3\().4s}, [KEY], #16
43 add T0.4s, T3.4s, \k0\().4s
44 add T1.4s, T3.4s, \k1\().4s
45 add T2.4s, T3.4s, \k2\().4s
46 add T3.4s, T3.4s, \k3\().4s
53 umlal PASS0_SUMS.2d, T0.2s, T4.2s
54 umlal PASS1_SUMS.2d, T1.2s, T5.2s
55 umlal PASS2_SUMS.2d, T2.2s, T6.2s
56 umlal PASS3_SUMS.2d, T3.2s, T7.2s
63 * It's guaranteed that message_len % 16 == 0.
[all …]
/kernel/linux/linux-5.10/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
68 #define XCHAL_NCP_SA_ALIGN 4
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
115 #define XCHAL_NCP_SA_LIST(s) \ argument
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
[all …]
/kernel/linux/linux-6.6/arch/xtensa/variants/test_kc705_hifi/include/variant/
Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
68 #define XCHAL_NCP_SA_ALIGN 4
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
115 #define XCHAL_NCP_SA_LIST(s) \ argument
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
[all …]
/kernel/linux/linux-5.10/drivers/watchdog/
Dsbc8360.c76 * MOV AX,000nH (set multiplier n, from 1-4)
95 * M | 1 2 3 4
97 * 0 | 0.5s 5s 50s 100s
98 * 1 | 1s 10s 100s 200s
99 * 2 | 1.5s 15s 150s 300s
100 * 3 | 2s 20s 200s 400s
101 * 4 | 2.5s 25s 250s 500s
102 * 5 | 3s 30s 300s 600s
103 * 6 | 3.5s 35s 350s 700s
104 * 7 | 4s 40s 400s 800s
[all …]
/kernel/linux/linux-6.6/drivers/watchdog/
Dsbc8360.c76 * MOV AX,000nH (set multiplier n, from 1-4)
95 * M | 1 2 3 4
97 * 0 | 0.5s 5s 50s 100s
98 * 1 | 1s 10s 100s 200s
99 * 2 | 1.5s 15s 150s 300s
100 * 3 | 2s 20s 200s 400s
101 * 4 | 2.5s 25s 250s 500s
102 * 5 | 3s 30s 300s 600s
103 * 6 | 3.5s 35s 350s 700s
104 * 7 | 4s 40s 400s 800s
[all …]
/kernel/linux/linux-5.10/arch/xtensa/variants/test_kc705_be/include/variant/
Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
68 #define XCHAL_NCP_SA_ALIGN 4
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
115 #define XCHAL_NCP_SA_LIST(s) \ argument
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
[all …]
/kernel/linux/linux-6.6/arch/xtensa/variants/test_kc705_be/include/variant/
Dtie.h7 /* This header file describes this specific Xtensa processor's TIE extensions
68 #define XCHAL_NCP_SA_ALIGN 4
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
115 #define XCHAL_NCP_SA_LIST(s) \ argument
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
[all …]
/kernel/linux/linux-6.6/arch/powerpc/crypto/
Dchacha-p10le-8x.S17 # 4. c += d; b ^= c; b <<<= 7
24 # 4 blocks (a b c d)
198 vadduwm 0, 0, 4
224 vxor 4, 4, 8
235 vrlw 4, 4, 25 #
244 vadduwm 0, 0, 4
274 vxor 4, 4, 8
282 vrlw 4, 4, 28 #
298 vadduwm 3, 3, 4
325 vxor 4, 4, 9
[all …]
/kernel/linux/linux-5.10/arch/xtensa/variants/dc232b/include/variant/
Dtie.h2 * This header file describes this specific Xtensa processor's TIE extensions
46 #define XCHAL_NCP_SA_ALIGN 4
50 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
57 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
60 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
82 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
93 #define XCHAL_NCP_SA_LIST(s) \ argument
94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
[all …]

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