| /kernel/linux/linux-6.6/tools/testing/selftests/mm/ |
| D | mremap_dontunmap.c | 40 // Try a simple operation for to "test" for kernel support this prevents
97 unsigned long num_pages = 5; in mremap_dontunmap_simple()
104 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple()
113 // the dest_mapping contains a's. in mremap_dontunmap_simple()
115 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple()
127 // This test validates that MREMAP_DONTUNMAP on a shared mapping works as expected.
130 unsigned long num_pages = 5; in mremap_dontunmap_simple_shmem()
145 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple_shmem()
161 // the dest_mapping contains a's. in mremap_dontunmap_simple_shmem()
163 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple_shmem()
[all …]
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| /kernel/linux/linux-5.10/tools/testing/selftests/vm/ |
| D | mremap_dontunmap.c | 43 // Try a simple operation for to "test" for kernel support this prevents
100 unsigned long num_pages = 5; in mremap_dontunmap_simple()
107 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple()
116 // the dest_mapping contains a's. in mremap_dontunmap_simple()
118 (dest_mapping, num_pages * page_size, 'a') != 0, in mremap_dontunmap_simple()
130 // This test validates MREMAP_DONTUNMAP will move page tables to a specific
135 unsigned long num_pages = 5; in mremap_dontunmap_simple_fixed()
137 // Since we want to guarantee that we can remap to a point, we will in mremap_dontunmap_simple_fixed()
138 // create a mapping up front. in mremap_dontunmap_simple_fixed()
149 memset(source_mapping, 'a', num_pages * page_size); in mremap_dontunmap_simple_fixed()
[all …]
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| /kernel/linux/linux-6.6/arch/alpha/lib/ |
| D | ev6-memset.S | 23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
41 .align 5
48 * undertake a major re-write to interleave the constant materialization
64 inswl $17,4,$5 # U : 0000chch00000000
69 or $2,$5,$2 # E : chchchch00000000
70 bic $1,7,$1 # E : fit within a single quadword?
79 * Target address is misaligned, and won't fit within a quadword
82 bis $16,$16,$5 # E : Save the address
92 stq_u $1,0($5) # L : Store result
[all …]
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| /kernel/linux/linux-5.10/arch/alpha/lib/ |
| D | ev6-memset.S | 23 * A future enhancement might be to put in a byte store loop for really
25 * a win in the kernel would depend upon the contextual usage.
41 .align 5
48 * undertake a major re-write to interleave the constant materialization
64 inswl $17,4,$5 # U : 0000chch00000000
69 or $2,$5,$2 # E : chchchch00000000
70 bic $1,7,$1 # E : fit within a single quadword?
79 * Target address is misaligned, and won't fit within a quadword
82 bis $16,$16,$5 # E : Save the address
92 stq_u $1,0($5) # L : Store result
[all …]
|
| /kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/ |
| D | pixfmt-packed-yuv.rst | 45 - 5
54 - 5
63 - 5
72 - 5
93 - a\ :sub:`3`
94 - a\ :sub:`2`
95 - a\ :sub:`1`
96 - a\ :sub:`0`
118 - a
147 - Cb\ :sub:`5`
[all …]
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| D | pixfmt-rgb.rst | 14 These are all packed-pixel formats, meaning all the data for a pixel lie
40 - 5
49 - 5
58 - 5
67 - 5
101 - a\ :sub:`3`
102 - a\ :sub:`2`
103 - a\ :sub:`1`
104 - a\ :sub:`0`
142 - a\ :sub:`3`
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylake/ |
| D | virtual-memory.json | 3 …"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/…
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
13 …sed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
19 "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
23 … in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.",
29 "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
30 "CounterHTOff": "0,1,2,3,4,5,6,7"
33 …sed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
39 "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
[all …]
|
| D | pipeline.json | 3 …a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable …
12 …a halt state. The thread enters the halt state when it is running the HLT instruction. This event …
30 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i…
39 …a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible …
46 "CounterHTOff": "0,1,2,3,4,5,6,7"
56 "CounterHTOff": "0,1,2,3,4,5,6,7"
66 "CounterHTOff": "0,1,2,3,4,5,6,7"
76 "CounterHTOff": "0,1,2,3,4,5,6,7"
86 "CounterHTOff": "0,1,2,3,4,5,6,7"
95 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | virtual-memory.json | 3 "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 … in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.",
13 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruct…
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
18 …on": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an ins…
23 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
28 …e sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The…
35 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | virtual-memory.json | 5 "CounterHTOff": "0,1,2,3,4,5,6,7",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
17 …"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M…
22 "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
27 … in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.",
32 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruct…
34 "CounterHTOff": "0,1,2,3,4,5,6,7",
37 …on": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an ins…
42 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
[all …]
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| /kernel/linux/linux-5.10/Documentation/input/devices/ |
| D | elantech.rst | 22 5. Hardware version 2
57 combine a status packet with multiple head or motion packets. Hardware version
58 4 allows tracking up to 5 fingers.
60 Some Hardware version 3 and version 4 also have a trackpoint which uses a
67 Note that a mouse button is also associated with either the touchpad or the
68 trackpoint when a trackpoint is available. Disabling the Touchpad in xorg
101 Currently a value of "1" will turn on some basic debugging and a value of
107 generate quite a lot of data!
118 calculating a parity bit for the last 3 bytes of each packet. The driver
175 By echoing a hexadecimal value to a register it contents can be altered.
[all …]
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| D | alps.rst | 8 ALPS touchpads, called versions 1, 2, 3, 4, 5, 6, 7 and 8.
11 integrated into a variety of laptops and netbooks. These new touchpads
23 (Compatibility ID) definition as a way to uniquely identify the
24 different ALPS variants but there did not appear to be a 1:1 mapping.
32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
45 The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
51 Protocol versions 3 and 4 have a command mode that is used to read and write
52 one-byte device registers in a 16-bit address space. The command sequence
54 with 88-07 followed by a third byte. This third byte can be used to determine
59 While in command mode, register addresses can be set by first sending a
[all …]
|
| /kernel/linux/linux-6.6/Documentation/input/devices/ |
| D | elantech.rst | 22 5. Hardware version 2
57 combine a status packet with multiple head or motion packets. Hardware version
58 4 allows tracking up to 5 fingers.
60 Some Hardware version 3 and version 4 also have a trackpoint which uses a
67 Note that a mouse button is also associated with either the touchpad or the
68 trackpoint when a trackpoint is available. Disabling the Touchpad in xorg
101 Currently a value of "1" will turn on some basic debugging and a value of
107 generate quite a lot of data!
118 calculating a parity bit for the last 3 bytes of each packet. The driver
175 By echoing a hexadecimal value to a register it contents can be altered.
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/icelake/ |
| D | frontend.json | 23 "CounterMask": "5"
58 "CounterMask": "5"
110 …n": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The leg…
117 "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss."
143 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
150 … "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss."
154 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
156 "Counter": "0,1,2,3,4,5,6,7",
158 "PEBScounters": "0,1,2,3,4,5,6,7",
165 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
[all …]
|
| D | pipeline.json | 4 …ANY is counted by a designated fixed counter freeing up programmable counters to count other event…
15 …"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of sa…
21 …"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP …
25 …a halt state. The thread enters the halt state when it is running the HLT instruction. This event …
35 …a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT i…
45 …a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible …
67 …"PublicDescription": "Counts the number of times a load got blocked due to false dependencies in M…
80 "Counter": "0,1,2,3,4,5,6,7",
82 "PEBScounters": "0,1,2,3,4,5,6,7",
89 …ription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buf…
[all …]
|
| D | memory.json | 4 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
11 …"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on …
15 …nts the number Transactional Synchronization Extensions (TSX) Aborts due to a data capacity limita…
22 …"BriefDescription": "Speculatively counts the number TSX Aborts due to a data capacity limitation …
26 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/co…
33 …"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE pref…
37 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock …
48 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit b…
59 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an un…
81 "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | virtual-memory.json | 11 "CounterHTOff": "0,1,2,3,4,5,6,7"
16 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
20 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
27 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
31 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
42 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | virtual-memory.json | 11 "CounterHTOff": "0,1,2,3,4,5,6,7"
14 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
21 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
25 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
32 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
36 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
43 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | virtual-memory.json | 11 "CounterHTOff": "0,1,2,3,4,5,6,7"
16 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
20 … misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end …
22 "CounterHTOff": "0,1,2,3,4,5,6,7"
27 …: "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that compl…
31 …ses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can …
33 "CounterHTOff": "0,1,2,3,4,5,6,7"
38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
42 …misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end …
44 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| /kernel/linux/linux-5.10/arch/s390/lib/ |
| D | uaccess.c | 72 /* protect against a concurrent page table upgrade */ in enable_sacf_uaccess()
122 " jnh 5f\n" in copy_from_user_mvcos()
125 " j 5f\n" in copy_from_user_mvcos()
127 "5:\n" in copy_from_user_mvcos()
128 EX_TABLE(0b,2b) EX_TABLE(3b,5b) EX_TABLE(6b,2b) EX_TABLE(7b,5b) in copy_from_user_mvcos()
129 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) in copy_from_user_mvcos()
145 "7: jz 5f\n" in copy_from_user_mvcp()
151 " j 5f\n" in copy_from_user_mvcp()
161 "5: slgr %0,%0\n" in copy_from_user_mvcp()
165 : "+a" (size), "+a" (ptr), "+a" (x), "+a" (tmp1), "=a" (tmp2) in copy_from_user_mvcp()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/perf/ |
| D | hisi-pmu.rst | 27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
38 The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
53 $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
54 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
60 specified as a bitmap::
62 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
72 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
76 3. Datasrc allows the user to check where the data comes from. It is 5 bits.
79 - 5'b00001: comes from L3C in this die;
80 - 5'b01000: comes from L3C in the cross-die;
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/crypto/ |
| D | aes-tab-4k.S | 10 * crypto/aes_generic.c and are designed to be simply accessed by a combination
11 * of rlwimi/lwz instructions with a minimum of table registers (usually only
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
25 #define R(a, b, c, d) \ argument
26 0x##a##b##c##d, 0x##d##a##b##c, 0x##c##d##a##b, 0x##b##c##d##a
40 .long R(4d, ab, ab, e6), R(ec, 76, 76, 9a)
46 .long R(5f, a2, a2, fd), R(45, af, af, ea)
48 .long R(e4, 72, 72, 96), R(9b, c0, c0, 5b)
50 .long R(3d, 93, 93, ae), R(4c, 26, 26, 6a)
51 .long R(6c, 36, 36, 5a), R(7e, 3f, 3f, 41)
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/crypto/ |
| D | aes-tab-4k.S | 10 * crypto/aes_generic.c and are designed to be simply accessed by a combination
11 * of rlwimi/lwz instructions with a minimum of table registers (usually only
19 * This is a quite good tradeoff for low power devices (e.g. routers) without
25 #define R(a, b, c, d) \ argument
26 0x##a##b##c##d, 0x##d##a##b##c, 0x##c##d##a##b, 0x##b##c##d##a
40 .long R(4d, ab, ab, e6), R(ec, 76, 76, 9a)
46 .long R(5f, a2, a2, fd), R(45, af, af, ea)
48 .long R(e4, 72, 72, 96), R(9b, c0, c0, 5b)
50 .long R(3d, 93, 93, ae), R(4c, 26, 26, 6a)
51 .long R(6c, 36, 36, 5a), R(7e, 3f, 3f, 41)
[all …]
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| /kernel/linux/linux-5.10/arch/m68k/fpsp040/ |
| D | tbldo.S | 10 | index with a 10-bit index, with the first
54 .long smovcr |$00-5 fmovecr all
63 .long serror |$01-5 fint ERROR
72 .long serror |$02-5 fsinh ERROR
81 .long serror |$03-5 fintrz ERROR
90 .long serror |$04-5 ERROR - illegal extension
99 .long serror |$05-5 ERROR - illegal extension
108 .long serror |$06-5 flognp1 ERROR
117 .long serror |$07-5 ERROR - illegal extension
126 .long serror |$08-5 fetoxm1 ERROR
[all …]
|
| /kernel/linux/linux-6.6/arch/m68k/fpsp040/ |
| D | tbldo.S | 10 | index with a 10-bit index, with the first
54 .long smovcr |$00-5 fmovecr all
63 .long serror |$01-5 fint ERROR
72 .long serror |$02-5 fsinh ERROR
81 .long serror |$03-5 fintrz ERROR
90 .long serror |$04-5 ERROR - illegal extension
99 .long serror |$05-5 ERROR - illegal extension
108 .long serror |$06-5 flognp1 ERROR
117 .long serror |$07-5 ERROR - illegal extension
126 .long serror |$08-5 fetoxm1 ERROR
[all …]
|