| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | microchip,sparx5-serdes.yaml | 35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
36 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
37 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
45 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
46 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
47 * 5 Gbps (QSGMII/USGMII)
48 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
49 * 10 Gbps (10G-USGMII)
50 * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
57 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
[all …]
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| D | apm-xgene-phy.txt | 1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
48 0 = 1-2Gbps
49 1 = 2-4Gbps (1st tuple default)
50 2 = 4-8Gbps
51 3 = 8-15Gbps (2nd tuple default)
52 4 = 2.5-4Gbps
53 5 = 4-5Gbps
54 6 = 5-6Gbps
55 7 = 6-16Gbps (3rd tuple default)
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | apm-xgene-phy.txt | 1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
48 0 = 1-2Gbps
49 1 = 2-4Gbps (1st tuple default)
50 2 = 4-8Gbps
51 3 = 8-15Gbps (2nd tuple default)
52 4 = 2.5-4Gbps
53 5 = 4-5Gbps
54 6 = 5-6Gbps
55 7 = 6-16Gbps (3rd tuple default)
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| /kernel/linux/linux-5.10/drivers/scsi/mvsas/ |
| D | mv_94xx.h | 75 /* ports 5-7 follow after this */
81 /* ports 5-7 follow after this */
87 /* ports 5-7 follow after this */
146 MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
[all …]
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| /kernel/linux/linux-6.6/drivers/scsi/mvsas/ |
| D | mv_94xx.h | 75 /* ports 5-7 follow after this */
81 /* ports 5-7 follow after this */
87 /* ports 5-7 follow after this */
146 MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
180 * bit 2: 6Gbps support
181 * bit 1: 3Gbps support
182 * bit 0: 1.5Gbps support
188 * bit 5: G1 (1.5Gbps) Without SSC
189 * bit 4: G1 (1.5Gbps) with SSC
190 * bit 3: G2 (3.0Gbps) Without SSC
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/ |
| D | dc_dp_types.h | 49 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
50 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
51 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
52 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
53 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane
54 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
55 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane
56 LINK_RATE_HIGH3 = 0x1E // Rate_8 (HBR3)- 8.10 Gbps/Lane
146 uint8_t MAX_LANE_COUNT:5;
157 uint8_t RESERVED:5;
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/ |
| D | dc_dp_types.h | 50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/ezchip/ |
| D | nps_enet.h | 59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
71 #define CFG_0_RX_FC_EN_SHIFT 5
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
129 #define CFG_3_CF_DROP_SHIFT 5
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| /kernel/linux/linux-5.10/drivers/net/ethernet/ezchip/ |
| D | nps_enet.h | 59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
71 #define CFG_0_RX_FC_EN_SHIFT 5
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
129 #define CFG_3_CF_DROP_SHIFT 5
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/ |
| D | smu11_driver_if_arcturus.h | 61 #define FEATURE_DPM_MP0CLK_BIT 5
192 #define THROTTLER_TEMP_VR_MEM_BIT 5
217 #define WORKLOAD_PPLIB_COUNT 5
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
435 XGMI_LINK_RATE_18 = 18, // 18Gbps
[all …]
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| D | smu11_driver_if_sienna_cichlid.h | 81 #define FEATURE_DPM_SOCCLK_BIT 5
199 #define THROTTLER_TEMP_VR_MEM0_BIT 5
222 #define FW_DSTATE_MP1_DS_BIT 5
431 #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5
501 XGMI_LINK_RATE_2 = 2, // 2Gbps
502 XGMI_LINK_RATE_4 = 4, // 4Gbps
503 XGMI_LINK_RATE_8 = 8, // 8Gbps
504 XGMI_LINK_RATE_12 = 12, // 12Gbps
505 XGMI_LINK_RATE_16 = 16, // 16Gbps
506 XGMI_LINK_RATE_17 = 17, // 17Gbps
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu11_driver_if_arcturus.h | 61 #define FEATURE_DPM_MP0CLK_BIT 5
192 #define THROTTLER_TEMP_VR_MEM_BIT 5
217 #define WORKLOAD_PPLIB_COUNT 5
429 XGMI_LINK_RATE_2 = 2, // 2Gbps
430 XGMI_LINK_RATE_4 = 4, // 4Gbps
431 XGMI_LINK_RATE_8 = 8, // 8Gbps
432 XGMI_LINK_RATE_12 = 12, // 12Gbps
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
434 XGMI_LINK_RATE_17 = 17, // 17Gbps
435 XGMI_LINK_RATE_18 = 18, // 18Gbps
[all …]
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| D | smu11_driver_if_sienna_cichlid.h | 81 #define FEATURE_DPM_SOCCLK_BIT 5
200 #define THROTTLER_TEMP_VR_MEM0_BIT 5
224 #define FW_DSTATE_MP1_DS_BIT 5
453 #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5
524 XGMI_LINK_RATE_2 = 2, // 2Gbps
525 XGMI_LINK_RATE_4 = 4, // 4Gbps
526 XGMI_LINK_RATE_8 = 8, // 8Gbps
527 XGMI_LINK_RATE_12 = 12, // 12Gbps
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
529 XGMI_LINK_RATE_17 = 17, // 17Gbps
[all …]
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| /kernel/linux/linux-6.6/tools/testing/selftests/drivers/net/mlxsw/ |
| D | qos_lib.sh | 29 # 1Gbps. That wouldn't saturate egress and MC would thus get through,
30 # seemingly winning bandwidth on account of UC. Demand at least 2Gbps
34 for i in {5..0}; do
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| D | qos_mc_aware.sh | 39 # | >1Gbps | | >1Gbps |
48 # | | 1Gbps bottleneck |
152 devlink_port_pool_th_set $swp1 0 5
154 devlink_tc_bind_pool_th_set $swp1 0 ingress 0 5
157 devlink_port_pool_th_set $swp2 0 5
159 devlink_tc_bind_pool_th_set $swp2 1 ingress 0 5
267 # degradation on 1Gbps link.
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| /kernel/linux/linux-6.6/drivers/net/phy/ |
| D | phy-core.c | 27 return "1Gbps"; in phy_speed_to_str()
29 return "2.5Gbps"; in phy_speed_to_str()
31 return "5Gbps"; in phy_speed_to_str()
33 return "10Gbps"; in phy_speed_to_str()
35 return "14Gbps"; in phy_speed_to_str()
37 return "20Gbps"; in phy_speed_to_str()
39 return "25Gbps"; in phy_speed_to_str()
41 return "40Gbps"; in phy_speed_to_str()
43 return "50Gbps"; in phy_speed_to_str()
45 return "56Gbps"; in phy_speed_to_str()
[all …]
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| /kernel/linux/linux-5.10/tools/testing/selftests/drivers/net/mlxsw/ |
| D | qos_mc_aware.sh | 39 # | >1Gbps | | >1Gbps |
48 # | | 1Gbps bottleneck |
149 devlink_port_pool_th_set $swp1 0 5
151 devlink_tc_bind_pool_th_set $swp1 0 ingress 0 5
154 devlink_port_pool_th_set $swp2 0 5
156 devlink_tc_bind_pool_th_set $swp2 1 ingress 0 5
264 # degradation on 1Gbps link.
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| D | qos_lib.sh | 29 # 1Gbps. That wouldn't saturate egress and MC would thus get through,
30 # seemingly winning bandwidth on account of UC. Demand at least 2Gbps
34 for i in {5..0}; do
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| /kernel/linux/linux-6.6/include/rdma/ |
| D | opa_port_info.h | 32 #define OPA_LINKDOWN_REASON_BAD_SLID 5
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
108 #define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5)
164 OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5),
181 OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5),
225 OPA_PI_MASK_VL_STALL = (0x03 << 5),
259 u8 cap; /* 3 res, 5 bits */
270 u8 smsl; /* 3 res, 5 bits */
[all …]
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| /kernel/linux/linux-5.10/include/rdma/ |
| D | opa_port_info.h | 32 #define OPA_LINKDOWN_REASON_BAD_SLID 5
96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */
97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */
98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */
108 #define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5)
164 OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5),
181 OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5),
225 OPA_PI_MASK_VL_STALL = (0x03 << 5),
259 u8 cap; /* 3 res, 5 bits */
270 u8 smsl; /* 3 res, 5 bits */
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 34 link_status[3], link_status[4], link_status[5]); in intel_dp_dump_link_status()
225 * x 5 identical voltage retries). Since the previous specs didn't in intel_dp_link_training_clock_recovery()
250 if (voltage_tries == 5) { in intel_dp_link_training_clock_recovery()
252 "Same voltage tried 5 times\n"); in intel_dp_link_training_clock_recovery()
308 "8.1 Gbps link rate without source HBR3/TPS4 support\n"); in intel_dp_training_pattern()
311 "8.1 Gbps link rate without sink TPS4 support\n"); in intel_dp_training_pattern()
325 ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); in intel_dp_training_pattern()
328 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); in intel_dp_training_pattern()
355 for (tries = 0; tries < 5; tries++) { in intel_dp_link_training_channel_equalization()
391 /* Try 5 times, else fail and try at lower BW */ in intel_dp_link_training_channel_equalization()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
| D | hclge_main.h | 138 #define HCLGE_PHY_MDIX_CTRL_S 5
139 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
172 #define HCLGE_RESET_INT_M GENMASK(7, 5)
177 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
188 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
201 #define HCLGE_SUPPORT_40G_BIT BIT(5)
239 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
240 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
241 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
242 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
[all …]
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| /kernel/linux/linux-5.10/drivers/net/phy/ |
| D | phy-core.c | 27 return "1Gbps"; in phy_speed_to_str()
29 return "2.5Gbps"; in phy_speed_to_str()
31 return "5Gbps"; in phy_speed_to_str()
33 return "10Gbps"; in phy_speed_to_str()
35 return "14Gbps"; in phy_speed_to_str()
37 return "20Gbps"; in phy_speed_to_str()
39 return "25Gbps"; in phy_speed_to_str()
41 return "40Gbps"; in phy_speed_to_str()
43 return "50Gbps"; in phy_speed_to_str()
45 return "56Gbps"; in phy_speed_to_str()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/ |
| D | ocelot.txt | 27 5 are fixed as internal ports in the NXP LS1028A instantiation.
33 2.5Gbps port@4, but can be moved to the 1Gbps port@5, depending on the specific
49 * phy_mode = "internal": on ports 4 and 5
65 ethernet-switch@0,5 {
108 port@5 {
109 reg = <5>;
133 * phy_mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
134 * phy_mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
175 port@5 {
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| /kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
| D | hclge_main.h | 113 #define HCLGE_PHY_MDIX_CTRL_S 5
114 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
151 #define HCLGE_RESET_INT_M GENMASK(7, 5)
157 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
168 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
191 #define HCLGE_SUPPORT_40G_BIT BIT(5)
235 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
236 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
237 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
238 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
[all …]
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