Home
last modified time | relevance | path

Searched +full:6 +full:- +full:bit (Results 1 – 25 of 1173) sorted by relevance

12345678910>>...47

/kernel/linux/linux-5.10/include/linux/mfd/da9150/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * DA9150 MFD Driver - Registers
159 #define DA9150_WRITE_MODE_SHIFT 6
160 #define DA9150_WRITE_MODE_MASK BIT(6)
162 #define DA9150_REVERT_MASK BIT(7)
167 #define DA9150_SLEEP_STAT_SHIFT 6
168 #define DA9150_SLEEP_STAT_MASK (0x03 << 6)
172 #define DA9150_VFAULT_STAT_MASK BIT(0)
174 #define DA9150_TFAULT_STAT_MASK BIT(1)
178 #define DA9150_VDD33_STAT_MASK BIT(0)
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/da9150/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * DA9150 MFD Driver - Registers
159 #define DA9150_WRITE_MODE_SHIFT 6
160 #define DA9150_WRITE_MODE_MASK BIT(6)
162 #define DA9150_REVERT_MASK BIT(7)
167 #define DA9150_SLEEP_STAT_SHIFT 6
168 #define DA9150_SLEEP_STAT_MASK (0x03 << 6)
172 #define DA9150_VFAULT_STAT_MASK BIT(0)
174 #define DA9150_TFAULT_STAT_MASK BIT(1)
178 #define DA9150_VDD33_STAT_MASK BIT(0)
[all …]
/kernel/linux/linux-5.10/Documentation/input/devices/
Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
24 5.2 Native absolute mode 6 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
28 6. Hardware version 3
30 6.2 Native absolute mode 6 byte packet format
35 7.2 Native absolute mode 6 byte packet format
41 8.2 Native relative mode 6 byte packet format
52 packet. Version 2 seems to be introduced with the EeePC and uses 6 bytes
54 and width of the touch. Hardware version 3 uses 6 bytes per packet (and
55 for 2 fingers the concatenation of two 6 bytes packets) and allows tracking
[all …]
/kernel/linux/linux-6.6/Documentation/input/devices/
Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
24 5.2 Native absolute mode 6 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
28 6. Hardware version 3
30 6.2 Native absolute mode 6 byte packet format
35 7.2 Native absolute mode 6 byte packet format
41 8.2 Native relative mode 6 byte packet format
52 packet. Version 2 seems to be introduced with the EeePC and uses 6 bytes
54 and width of the touch. Hardware version 3 uses 6 bytes per packet (and
55 for 2 fingers the concatenation of two 6 bytes packets) and allows tracking
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/da9062/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
157 #define DA9062AA_WRITE_MODE_SHIFT 6
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/da9062/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
157 #define DA9062AA_WRITE_MODE_SHIFT 6
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/
Dlp87565.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
97 #define LP87565_BUCK_CTRL_1_EN BIT(7)
98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
119 #define LP87565_RESET_SW_RESET BIT(0)
121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/microchip/
Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
49 #define SW_GIGABIT_ABLE BIT(6)
50 #define SW_REDUNDANCY_ABLE BIT(5)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
[all …]
Dksz8795_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
34 #define SW_NEW_BACKOFF BIT(7)
35 #define SW_GLOBAL_RESET BIT(6)
36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
38 #define SW_LINK_AUTO_AGING BIT(0)
42 #define SW_HUGE_PACKET BIT(6)
43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)
45 #define SW_CHECK_LENGTH BIT(3)
[all …]
/kernel/linux/linux-5.10/drivers/usb/typec/tcpm/
Dfusb302_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2017 Google, Inc
5 * Fairchild FUSB302 Type-C Chip Driver
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
[all …]
/kernel/linux/linux-6.6/drivers/usb/typec/tcpm/
Dfusb302_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2017 Google, Inc
5 * Fairchild FUSB302 Type-C Chip Driver
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
[all …]
/kernel/linux/linux-6.6/drivers/net/dsa/microchip/
Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2024 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define PME_ENABLE BIT(1)
44 #define PME_POLARITY BIT(0)
48 #define SW_GIGABIT_ABLE BIT(6)
49 #define SW_REDUNDANCY_ABLE BIT(5)
50 #define SW_AVB_ABLE BIT(4)
68 #define SW_QW_ABLE BIT(5)
74 #define LUE_INT BIT(31)
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/
Dlp87565.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
97 #define LP87565_BUCK_CTRL_1_EN BIT(7)
98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
102 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
103 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
119 #define LP87565_RESET_SW_RESET BIT(0)
121 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
[all …]
/kernel/linux/linux-6.6/Documentation/userspace-api/media/rc/
Drc-protos.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
38 .. flat-table:: rc5 bits scancode mapping
41 * - rc-5 bit
43 - scancode bit
45 - description
[all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/rc/
Drc-protos.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
38 .. flat-table:: rc5 bits scancode mapping
41 * - rc-5 bit
43 - scancode bit
45 - description
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dtas6424.h1 // SPDX-License-Identifier: GPL-2.0
3 * ALSA SoC Texas Instruments TAS6424 Quad-Channel Audio Amplifier
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
57 #define TAS6424_RESET BIT(7)
60 #define TAS6424_SAP_RATE_MASK GENMASK(7, 6)
61 #define TAS6424_SAP_RATE_44100 (0x00 << 6)
62 #define TAS6424_SAP_RATE_48000 (0x01 << 6)
63 #define TAS6424_SAP_RATE_96000 (0x02 << 6)
64 #define TAS6424_SAP_TDM_SLOT_LAST BIT(5)
65 #define TAS6424_SAP_TDM_SLOT_SZ_16 BIT(4)
[all …]
Drk3328_codec.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 #define PWR_RST_BYPASS_DIS (0x0 << 6)
30 #define PWR_RST_BYPASS_EN (0x1 << 6)
37 #define PIN_DIRECTION_MASK BIT(5)
40 #define DAC_I2S_MODE_MASK BIT(4)
45 #define DAC_I2S_LRP_MASK BIT(7)
48 #define DAC_VDL_MASK GENMASK(6, 5)
58 #define DAC_LR_SWAP_MASK BIT(2)
68 #define DAC_RST_MASK BIT(1)
71 #define DAC_BCP_MASK BIT(0)
[all …]
/kernel/linux/linux-6.6/sound/soc/codecs/
Dtas6424.h1 // SPDX-License-Identifier: GPL-2.0
3 * ALSA SoC Texas Instruments TAS6424 Quad-Channel Audio Amplifier
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
57 #define TAS6424_RESET BIT(7)
60 #define TAS6424_SAP_RATE_MASK GENMASK(7, 6)
61 #define TAS6424_SAP_RATE_44100 (0x00 << 6)
62 #define TAS6424_SAP_RATE_48000 (0x01 << 6)
63 #define TAS6424_SAP_RATE_96000 (0x02 << 6)
64 #define TAS6424_SAP_TDM_SLOT_LAST BIT(5)
65 #define TAS6424_SAP_TDM_SLOT_SZ_16 BIT(4)
[all …]
Drk3328_codec.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 #define PWR_RST_BYPASS_DIS (0x0 << 6)
30 #define PWR_RST_BYPASS_EN (0x1 << 6)
37 #define PIN_DIRECTION_MASK BIT(5)
40 #define DAC_I2S_MODE_MASK BIT(4)
45 #define DAC_I2S_LRP_MASK BIT(7)
48 #define DAC_VDL_MASK GENMASK(6, 5)
58 #define DAC_LR_SWAP_MASK BIT(2)
68 #define DAC_RST_MASK BIT(1)
71 #define DAC_BCP_MASK BIT(0)
[all …]
/kernel/linux/linux-5.10/include/soc/mscc/
Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
[all …]
/kernel/linux/linux-6.6/include/linux/soundwire/
Dsdw_registers.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
36 #define SDW_DP0_INT_TEST_FAIL BIT(0)
37 #define SDW_DP0_INT_PORT_READY BIT(1)
38 #define SDW_DP0_INT_BRA_FAILURE BIT(2)
39 #define SDW_DP0_SDCA_CASCADE BIT(3)
40 /* BIT(4) not allocated in SoundWire specification 1.2 */
41 #define SDW_DP0_INT_IMPDEF1 BIT(5)
42 #define SDW_DP0_INT_IMPDEF2 BIT(6)
43 #define SDW_DP0_INT_IMPDEF3 BIT(7)
[all …]
/kernel/linux/linux-5.10/include/linux/soundwire/
Dsdw_registers.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
36 #define SDW_DP0_INT_TEST_FAIL BIT(0)
37 #define SDW_DP0_INT_PORT_READY BIT(1)
38 #define SDW_DP0_INT_BRA_FAILURE BIT(2)
39 #define SDW_DP0_SDCA_CASCADE BIT(3)
40 /* BIT(4) not allocated in SoundWire specification 1.2 */
41 #define SDW_DP0_INT_IMPDEF1 BIT(5)
42 #define SDW_DP0_INT_IMPDEF2 BIT(6)
43 #define SDW_DP0_INT_IMPDEF3 BIT(7)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
35 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
36 #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
37 #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
38 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
39 #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
40 #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
42 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
35 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
36 #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
37 #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
38 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
39 #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
40 #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
42 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/mcde/
Dmcde_dsi_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)
13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)
14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)
15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)
16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)
[all …]

12345678910>>...47