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/kernel/linux/linux-5.10/drivers/net/wireless/ath/wcn36xx/
Dtxrx.c65 { 65, 0, RX_ENC_HT, 0, RATE_INFO_BW_20 },
85 { 65, 0, RX_ENC_HT, RX_ENC_FLAG_HT_GF, RATE_INFO_BW_20 },
128 /* 11ac 20 MHz 800ns GI MCS 0-8 */
129 { 65, 0, RX_ENC_HT, 0, RATE_INFO_BW_20 },
150 /* 11ac 20 MHz 400ns SGI MCS 6-8 */
160 /* 11ac 40 MHz 800ns GI MCS 0-9 */
181 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
189 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
196 /* 11ac 80 MHz 800ns GI MCS 0-7 */
209 /* 11ac 80 MHz 800 ns GI MCS 8-9 */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Ddwc3-xilinx.yaml38 - description: Master/Core clock, has to be >= 125 MHz
39 for SS operation and >= 60MHz for HS operation.
130 interrupts = <0 65 4>, <0 69 4>;
/kernel/linux/linux-5.10/arch/x86/kernel/cpu/
Dtransmeta.c27 char cpu_info[65]; in init_transmeta()
39 pr_info("CPU: Processor revision %u.%u.%u.%u, %u MHz\n", in init_transmeta()
50 pr_info("CPU: Processor revision %08X, %u MHz\n", in init_transmeta()
/kernel/linux/linux-6.6/arch/x86/kernel/cpu/
Dtransmeta.c27 char cpu_info[65]; in init_transmeta()
39 pr_info("CPU: Processor revision %u.%u.%u.%u, %u MHz\n", in init_transmeta()
50 pr_info("CPU: Processor revision %08X, %u MHz\n", in init_transmeta()
/kernel/linux/linux-6.6/drivers/net/wireless/ath/wcn36xx/
Dtxrx.c71 { 65, 0, RX_ENC_HT, 0, RATE_INFO_BW_20 },
91 { 65, 0, RX_ENC_HT, RX_ENC_FLAG_HT_GF, RATE_INFO_BW_20 },
134 /* 11ac 20 MHz 800ns GI MCS 0-8 */
135 { 65, 0, RX_ENC_HT, 0, RATE_INFO_BW_20 },
156 /* 11ac 20 MHz 400ns SGI MCS 6-8 */
166 /* 11ac 40 MHz 800ns GI MCS 0-9 */
187 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
195 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
202 /* 11ac 80 MHz 800ns GI MCS 0-7 */
215 /* 11ac 80 MHz 800 ns GI MCS 8-9 */
[all …]
/kernel/linux/linux-6.6/Documentation/hwmon/
Dadm1021.rst119 are possible between -65 and +127 degrees, with a resolution of one degree.
137 era (with 400 MHz FSB) had chips with only one temperature sensor.
150 didn't have these sensors. Next generations of Xeon processors (533 MHz
/kernel/linux/linux-5.10/Documentation/hwmon/
Dadm1021.rst119 are possible between -65 and +127 degrees, with a resolution of one degree.
137 era (with 400 MHz FSB) had chips with only one temperature sensor.
150 didn't have these sensors. Next generations of Xeon processors (533 MHz
/kernel/linux/linux-5.10/drivers/clk/uniphier/
Dclk-uniphier-sys.c83 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
84 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
85 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
86 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
99 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
100 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
101 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
102 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
128 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/kernel/linux/linux-6.6/drivers/clk/spear/
Dspear1340_clock.c164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/kernel/linux/linux-5.10/drivers/clk/spear/
Dspear1340_clock.c167 /* PCLK 24MHz */
168 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
170 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
172 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
173 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
175 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
180 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
181 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dmpc5125twr.dts39 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
40 bus-frequency = <198000000>; // 198 MHz csb bus
41 clock-frequency = <396000000>; // 396 MHz ppc core
72 bus-frequency = <66000000>; // 66 MHz ips bus
289 interrupts = <65 0x8>;
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/
Dmpc5125twr.dts39 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
40 bus-frequency = <198000000>; // 198 MHz csb bus
41 clock-frequency = <396000000>; // 396 MHz ppc core
72 bus-frequency = <66000000>; // 66 MHz ips bus
289 interrupts = <65 0x8>;
/kernel/linux/linux-6.6/drivers/clk/uniphier/
Dclk-uniphier-sys.c87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
132 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
Dmxl5xx_defs.h99 MXL_XCPU_PID_FLT_CFG_CMD = 65,
396 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
397 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
398 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
399 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
404 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
433 MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Dmxl5xx_defs.h103 MXL_XCPU_PID_FLT_CFG_CMD = 65,
400 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
405 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
406 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
407 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
408 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
437 MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
[all …]
/kernel/linux/linux-5.10/drivers/clk/versatile/
Dclk-icst.c107 * 33 or 25 MHz respectively. in vco_get()
262 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_round_rate()
267 /* Slam to closest 0.25 MHz */ in icst_round_rate()
273 * If we're below or less than halfway from 25 to 33 MHz in icst_round_rate()
274 * select 25 MHz in icst_round_rate()
415 .rd_max = 65,
438 /* Minimum 12 MHz, VDW = 4 */
441 * Maximum 160 MHz, VDW = 152 for all core modules, but
443 * go to 200 MHz (max VDW = 192).
456 /* Minimum 3 MHz, VDW = 4 */
[all …]
/kernel/linux/linux-6.6/drivers/clk/versatile/
Dclk-icst.c108 * 33 or 25 MHz respectively. in vco_get()
263 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_round_rate()
268 /* Slam to closest 0.25 MHz */ in icst_round_rate()
274 * If we're below or less than halfway from 25 to 33 MHz in icst_round_rate()
275 * select 25 MHz in icst_round_rate()
416 .rd_max = 65,
439 /* Minimum 12 MHz, VDW = 4 */
442 * Maximum 160 MHz, VDW = 152 for all core modules, but
444 * go to 200 MHz (max VDW = 192).
457 /* Minimum 3 MHz, VDW = 4 */
[all …]
/kernel/linux/linux-6.6/drivers/media/tuners/
Dfc0012.c217 /* fix for frequency less than 45 MHz */ in fc0012_set_params()
348 -63, -65, -54, -60, in fc0012_get_rf_strength()
351 65, 63, 61, 58, in fc0012_get_rf_strength()
411 .frequency_min_hz = 37 * MHz, /* estimate */
412 .frequency_max_hz = 862 * MHz, /* estimate */
/kernel/linux/linux-5.10/drivers/media/tuners/
Dfc0012.c217 /* fix for frequency less than 45 MHz */ in fc0012_set_params()
348 -63, -65, -54, -60, in fc0012_get_rf_strength()
351 65, 63, 61, 58, in fc0012_get_rf_strength()
411 .frequency_min_hz = 37 * MHz, /* estimate */
412 .frequency_max_hz = 862 * MHz, /* estimate */
/kernel/linux/linux-6.6/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/kernel/linux/linux-5.10/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
Dcdv_intel_display.c56 /* The single-channel range is 25-112Mhz, and dual-channel
57 * is 80-224Mhz. Prefer single channel as much as possible.
68 .m2 = {.min = 65, .max = 130},
92 .m2 = {.min = 65, .max = 130},
625 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
628 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
635 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise in cdv_intel_crtc_mode_set()
636 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose in cdv_intel_crtc_mode_set()
637 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. in cdv_intel_crtc_mode_set()
647 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); in cdv_intel_crtc_mode_set()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
Dcdv_intel_display.c57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
69 .m2 = {.min = 65, .max = 130},
93 .m2 = {.min = 65, .max = 130},
628 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
631 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
638 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise in cdv_intel_crtc_mode_set()
639 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose in cdv_intel_crtc_mode_set()
640 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. in cdv_intel_crtc_mode_set()
650 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); in cdv_intel_crtc_mode_set()
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-vt8500.c380 * Where O1 is 900MHz...3GHz;
381 * O2 is 600MHz >= (M * parent) / P >= 300MHz;
382 * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
384 * D = 8: 37,5MHz...75MHz
385 * D = 4: 75MHz...150MHz
386 * D = 2: 150MHz...300MHz
387 * D = 1: 300MHz...600MHz
427 /* calculate frequency (MHz) after pre-divisor */ in wm8750_get_filter()
431 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n", in wm8750_get_filter()
438 else if (freq >= 65) in wm8750_get_filter()
/kernel/linux/linux-6.6/drivers/clk/
Dclk-vt8500.c380 * Where O1 is 900MHz...3GHz;
381 * O2 is 600MHz >= (M * parent) / P >= 300MHz;
382 * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
384 * D = 8: 37,5MHz...75MHz
385 * D = 4: 75MHz...150MHz
386 * D = 2: 150MHz...300MHz
387 * D = 1: 300MHz...600MHz
427 /* calculate frequency (MHz) after pre-divisor */ in wm8750_get_filter()
431 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n", in wm8750_get_filter()
438 else if (freq >= 65) in wm8750_get_filter()

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