| /kernel/linux/linux-5.10/drivers/ptp/ |
| D | ptp_clockmatrix.c | 1 // SPDX-License-Identifier: GPL-2.0+
23 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
29 * over-rides any automatic selection
38 struct idtcm_channel *channel = in set_write_phase_ready() local
41 channel->write_phase_ready = 1; in set_write_phase_ready()
57 /* Sub-nanoseconds are in buf[0]. */ in char_array_to_timespec()
60 nsec <<= 8; in char_array_to_timespec()
61 nsec |= buf[3 - i]; in char_array_to_timespec()
66 sec <<= 8; in char_array_to_timespec()
67 sec |= buf[9 - i]; in char_array_to_timespec()
[all …]
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| /kernel/linux/linux-6.6/include/sound/ |
| D | ump_msg.h | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* MIDI 1.0 Channel Control (7bit) */
36 UMP_CC_BALANCE = 8,
134 u32 channel:4; member
135 u32 note:8;
136 u32 velocity:8;
138 u32 velocity:8;
139 u32 note:8;
140 u32 channel:4;
153 u32 channel:4; member
[all …]
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| /kernel/linux/linux-5.10/sound/core/oss/ |
| D | linear.c | 2 * Linear conversion Plug-In
4 * Abramo Bagnara <abramo@alsa-project.org>
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 memcpy(p + data->copy_ofs, src + data->src_ofs, data->copy_bytes); in do_convert()
49 if (data->cvt_endian) in do_convert()
51 tmp ^= data->flip; in do_convert()
52 memcpy(dst, p + data->dst_ofs, data->dst_bytes); in do_convert()
60 struct linear_priv *data = (struct linear_priv *)plugin->extra_data; in convert()
61 int channel; in convert() local
62 int nchannels = plugin->src_format.channels; in convert()
[all …]
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| D | mulaw.c | 2 * Mu-Law conversion Plug-In Interface
4 * Uros Bizjak <uros@kss-loka.si>
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define SIGN_BIT (0x80) /* Sign bit for a u-law byte. */
31 #define NSEGS (8) /* Number of u-law segments. */
55 * linear2ulaw() - Convert a linear PCM value to u-law
58 * is biased by adding 33 which shifts the encoding range from (0 - 8158) to
59 * (33 - 8191). The result can be seen in the following encoding table:
62 * ------------------------ ---------------
75 * four bits wxyz. * The trailing bits (a - h) are ignored.
[all …]
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| D | rate.c | 2 * Rate conversion Plug-In
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define R_MASK (BITS-1)
55 unsigned int channel; in rate_init() local
56 struct rate_priv *data = (struct rate_priv *)plugin->extra_data; in rate_init()
57 data->pos = 0; in rate_init()
58 for (channel = 0; channel < plugin->src_format.channels; channel++) { in rate_init()
59 data->channels[channel].last_S1 = 0; in rate_init()
60 data->channels[channel].last_S2 = 0; in rate_init()
73 unsigned int channel; in resample_expand() local
[all …]
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| /kernel/linux/linux-6.6/sound/core/oss/ |
| D | linear.c | 2 * Linear conversion Plug-In
4 * Abramo Bagnara <abramo@alsa-project.org>
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 memcpy(p + data->copy_ofs, src + data->src_ofs, data->copy_bytes); in do_convert()
49 if (data->cvt_endian) in do_convert()
51 tmp ^= data->flip; in do_convert()
52 memcpy(dst, p + data->dst_ofs, data->dst_bytes); in do_convert()
60 struct linear_priv *data = (struct linear_priv *)plugin->extra_data; in convert()
61 int channel; in convert() local
62 int nchannels = plugin->src_format.channels; in convert()
[all …]
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| D | rate.c | 2 * Rate conversion Plug-In
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define R_MASK (BITS-1)
55 unsigned int channel; in rate_init() local
56 struct rate_priv *data = (struct rate_priv *)plugin->extra_data; in rate_init()
57 data->pos = 0; in rate_init()
58 for (channel = 0; channel < plugin->src_format.channels; channel++) { in rate_init()
59 data->channels[channel].last_S1 = 0; in rate_init()
60 data->channels[channel].last_S2 = 0; in rate_init()
73 unsigned int channel; in resample_expand() local
[all …]
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| D | mulaw.c | 2 * Mu-Law conversion Plug-In Interface
4 * Uros Bizjak <uros@kss-loka.si>
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define SIGN_BIT (0x80) /* Sign bit for a u-law byte. */
31 #define NSEGS (8) /* Number of u-law segments. */
55 * linear2ulaw() - Convert a linear PCM value to u-law
58 * is biased by adding 33 which shifts the encoding range from (0 - 8158) to
59 * (33 - 8191). The result can be seen in the following encoding table:
62 * ------------------------ ---------------
75 * four bits wxyz. * The trailing bits (a - h) are ignored.
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/bcm/ |
| D | clk-ns2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
49 .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
52 .mdiv = REG_VAL(0x18, 0, 8),
55 .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
58 .mdiv = REG_VAL(0x18, 8, 8),
61 .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
64 .mdiv = REG_VAL(0x14, 0, 8),
[all …]
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| D | clk-cygnus.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
63 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
66 .mdiv = REG_VAL(0x20, 0, 8),
69 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
72 .mdiv = REG_VAL(0x20, 10, 8),
75 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-ns2.c | 16 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/bcm-ns2.h>
22 #include "clk-iproc.h"
59 .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
62 .mdiv = REG_VAL(0x18, 0, 8),
65 .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
68 .mdiv = REG_VAL(0x18, 8, 8),
71 .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
74 .mdiv = REG_VAL(0x14, 0, 8),
77 .channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
[all …]
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| D | clk-cygnus.c | 16 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/bcm-cygnus.h>
24 #include "clk-iproc.h"
55 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
73 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
76 .mdiv = REG_VAL(0x20, 0, 8),
79 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
82 .mdiv = REG_VAL(0x20, 10, 8),
85 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
87 .enable = ENABLE_VAL(0x4, 8, 2, 14),
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
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| /kernel/linux/linux-5.10/sound/soc/sprd/ |
| D | sprd-mcdt.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
57 /* Channel water mark definition */
60 #define MCDT_CH_FIFO_AF_MASK GENMASK(8, 0)
62 /* DMA channel select definition */
67 #define MCDT_DMA_CH2_SEL_MASK GENMASK(11, 8)
68 #define MCDT_DMA_CH2_SEL_SHIFT 8
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
[all …]
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| /kernel/linux/linux-6.6/sound/soc/sprd/ |
| D | sprd-mcdt.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
57 /* Channel water mark definition */
60 #define MCDT_CH_FIFO_AF_MASK GENMASK(8, 0)
62 /* DMA channel select definition */
67 #define MCDT_DMA_CH2_SEL_MASK GENMASK(11, 8)
68 #define MCDT_DMA_CH2_SEL_SHIFT 8
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
[all …]
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| /kernel/linux/linux-6.6/drivers/hsi/controllers/ |
| D | omap_ssi_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
32 #define SSI_MPU_ENABLE_REG(port, irq) (0x80c + ((port) * 0x10) + ((irq) * 8))
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
57 #define SSI_SST_FRAMESIZE_REG 8
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
[all …]
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| /kernel/linux/linux-5.10/drivers/hsi/controllers/ |
| D | omap_ssi_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
32 #define SSI_MPU_ENABLE_REG(port, irq) (0x80c + ((port) * 0x10) + ((irq) * 8))
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
57 #define SSI_SST_FRAMESIZE_REG 8
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
[all …]
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| /kernel/linux/linux-6.6/Documentation/ABI/testing/ |
| D | configfs-most | 2 Date: March 8, 2019
9 # mount -t configfs none /sys/kernel/config/
13 Date: March 8, 2019
19 configure the buffer size for this channel
22 configure the sub-buffer size for this channel
28 channel
32 this channel
51 channel
52 name of the channel the link is to be attached to
60 configuration, the creation is post-poned until
[all …]
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| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | configfs-most | 2 Date: March 8, 2019
9 # mount -t configfs none /sys/kernel/config/
13 Date: March 8, 2019
19 configure the buffer size for this channel
22 configure the sub-buffer size for this channel
28 channel
32 this channel
51 channel
52 name of the channel the link is to be attached to
60 configuration, the creation is post-poned until
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/microchip/ |
| D | lan743x_main.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
32 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
64 #define PMT_CTL_RES_CLR_WKP_MASK_ GENMASK(9, 8)
131 #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8)
151 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
152 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
153 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
156 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
157 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
158 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt76x2/ |
| D | eeprom.c | 1 // SPDX-License-Identifier: ISC
17 void *src = dev->mt76.eeprom.data + MT_EE_MAC_ADDR; in mt76x2_eeprom_get_macaddr()
19 memcpy(dev->mt76.macaddr, src, ETH_ALEN); in mt76x2_eeprom_get_macaddr()
80 struct device_node *np = dev->mt76.dev->of_node; in mt76x2_apply_cal_free_data()
81 u8 *eeprom = dev->mt76.eeprom.data; in mt76x2_apply_cal_free_data()
91 if (!np || !of_property_read_bool(np, "mediatek,eeprom-merge-otp")) in mt76x2_apply_cal_free_data()
116 eeprom[MT_EE_BT_VCDL_CALIBRATION + 1] = val >> 8; in mt76x2_apply_cal_free_data()
125 u16 val = get_unaligned_le16(dev->mt76.eeprom.data); in mt76x2_check_eeprom()
128 val = get_unaligned_le16(dev->mt76.eeprom.data + MT_EE_PCI_ID); in mt76x2_check_eeprom()
135 dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n", val); in mt76x2_check_eeprom()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt76x2/ |
| D | eeprom.c | 1 // SPDX-License-Identifier: ISC
17 void *src = dev->mt76.eeprom.data + MT_EE_MAC_ADDR; in mt76x2_eeprom_get_macaddr()
19 memcpy(dev->mphy.macaddr, src, ETH_ALEN); in mt76x2_eeprom_get_macaddr()
80 struct device_node *np = dev->mt76.dev->of_node; in mt76x2_apply_cal_free_data()
81 u8 *eeprom = dev->mt76.eeprom.data; in mt76x2_apply_cal_free_data()
91 if (!np || !of_property_read_bool(np, "mediatek,eeprom-merge-otp")) in mt76x2_apply_cal_free_data()
116 eeprom[MT_EE_BT_VCDL_CALIBRATION + 1] = val >> 8; in mt76x2_apply_cal_free_data()
125 u16 val = get_unaligned_le16(dev->mt76.eeprom.data); in mt76x2_check_eeprom()
128 val = get_unaligned_le16(dev->mt76.eeprom.data + MT_EE_PCI_ID); in mt76x2_check_eeprom()
135 dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n", val); in mt76x2_check_eeprom()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | st,sta32x.txt | 7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
22 - clocks, clock-names: Clock specifier for XTI input clock.
24 and disabled when it is removed. The 'clock-names' must be set to 'xti'.
26 - st,output-conf: number, Selects the output configuration:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | st,sta32x.txt | 7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
22 - clocks, clock-names: Clock specifier for XTI input clock.
24 and disabled when it is removed. The 'clock-names' must be set to 'xti'.
26 - st,output-conf: number, Selects the output configuration:
[all …]
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