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/arkcompiler/runtime_core/static_core/plugins/ets/templates/stdlib/
D	DataView.ets.j2	2 * Copyright (c) 2021-2025 Huawei Device Co., Ltd. 7 * http://www.apache.org/licenses/LICENSE-2.0 47 this(buffer, byteOffset, (buffer as Buffer).getByteLength() - byteOffset) 76 …teOffset, 0), asIntOrDefault(byteLength, (buffer as Buffer).getByteLength() - asIntOrDefault(byteO… 79 {%- for bit in [8, 16, 32, 64] %} 80 {%- for mode in ["Int", "Uint", "Float"] %} 81 {%- if mode != "Float" or bit >= 32 %} 82 // === {{mode}}{{bit}} === 83 {%- set impls = ['Little', 'Big'] if bit != 8 else ['Big'] %} 85 {%- set type2nameBits = {8: "byte", 16: "short", 32: "int", 64: "long"} %} [all …]
/arkcompiler/runtime_core/docs/changelogs/
D	2022-08-18-isa-changelog.md	1 # 2022-08-18-isa-changelog 15 3. We add prefix "deprecated" and keep the many old isa as "deprecated"-prefixed opcodes (for compa… 20 8. We add 8-bit or 16-bit imm as inline cache slot for some specific opcodes. 23 As we merge some "define-function" opcodes as one opcode, in function we add one field which record… 24 such that runtime can distinguish the "define-function" operations of different kinds. 26 We reuse the field 32-bit field `access_flags_` to encode Function Kind and Header index. 27 This will not introduce compatibility issue because the later 24-bit of `access_flags_` is unused i… 30 \|<- 16-bit header index ->\|<- 8-bit function kind ->\|<- 8-bit original access flag ->\| 39 As we use 16-bit to encode methodId, stringId and literalarrayId, the number of these Ids in one me… 45 3. In bytecode, we still use 16-bit literalarrayId rather than offset. [all …]
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_ir/include/
D	cmpl.h	7 * http://www.apache.org/licenses/LICENSE-2.0 36 uint8 formalWordsTypetagged; // bit vector where the Nth bit tells whether 43 uint8 localWordsTypetagged; // bit vector where the Nth bit tells whether 46 // the word at location (%%FP - N4)) has 48 // at (%%FP - N4 + 4); the bitvector's size 50 uint8 formalWordsRefCounted; // bit vector where the Nth bit tells whether 57 uint8 localWordsRefCounted; // bit vector where the Nth bit tells whether 60 // the word at location (%%FP - N4)) points to 76 return funcSize - (kTwoBitVectors BlockSize2BitVectorSize(upFormalSize)) - in FuncCodeSize() 89 uint8 *globalWordsTypetagged; // bit vector where the Nth bit tells whether [all …]
/arkcompiler/runtime_core/static_core/verification/util/
D	mem.h	2 * Copyright (c) 2022-2024 Huawei Device Co., Ltd. 7 * http://www.apache.org/licenses/LICENSE-2.0 24 is unavailable for allocation -- for example, it may be reserved for kernel memory. 27 https://linux-kernel-labs.github.io/refs/heads/master/lectures/address-space.html 29 Linux is using a split address space for 32 bit systems, although in the past there 31 …architecture that supports it, e.g. x86). Linux always uses split address space for 64 bit systems. 33 [For 32-bit Linux, the split is usually 3/1, i.e. 0x00000000-0xc0000000 is user space, 34 0xc0000000-0xffffffff is kernel space] 36 …For Windows: https://learn.microsoft.com/en-us/windows-hardware/drivers/gettingstarted/virtual-add… 38 For a 32-bit process, the virtual address space is usually the 2-gigabyte range 0x00000000 [all …]
/arkcompiler/runtime_core/static_core/plugins/ets/tests/ets_sdk/arkts/@arkts/collections/BitVector/
D	getBitsByRangeTests.ets	7 * http://www.apache.org/licenses/LICENSE-2.0 25 …suite.addTest("Returns the bit values in a valid range of indices.", BitVector_getBitsByRange_Func… 27 … suite.addTest("Throws an error for non-integer 'fromIndex'.", BitVector_getBitsByRange_Func_003); 30 suite.addTest("Returns the bit values in a large range.", BitVector_getBitsByRange_Func_006); 31 …suite.addTest("Returns the bit values in a range with an initial length.", BitVector_getBitsByRang… 39 * @tc.desc : Returns the bit values in a valid range of indices in a bit vector. 52 assertEQ(result[0], 1, "Bit at index 0 should be 1"); 53 assertEQ(result[1], 1, "Bit at index 1 should be 1"); 54 assertEQ(result[2], 0, "Bit at index 2 should be 0"); 60 * @tc.desc : Throws an error for invalid 'toIndex' range in a bit vector. [all …]
D	hasTests.ets	7 * http://www.apache.org/licenses/LICENSE-2.0 25 …suite.addTest("Verify if bit vector correctly identifies bit values within a specified range.", Bi… 26 …suite.addTest("Verify that bit vector throws an error when toIndex is negative.", BitVector_has_Fu… 27 …suite.addTest("Verify that bit vector throws an error when fromIndex is not an integer.", BitVecto… 28 …suite.addTest("Verify that bit vector throws an error when both fromIndex and toIndex are negative… 29 …suite.addTest("Verify that bit vector throws an error when fromIndex is negative while toIndex is … 30 …suite.addTest("Verify if bit vector correctly identifies bit values in a large range spanning mult… 31 …suite.addTest("Verify if bit vector with initial length correctly identifies bit values across its… 32 …suite.addTest("Verify that bit vector throws an error when fromIndex is greater than toIndex.", Bi… 33 …suite.addTest("Verify if bit vector correctly identifies bit values in a single-element range.", B… [all …]
D	setBitsByRangeTests.ets	7 * http://www.apache.org/licenses/LICENSE-2.0 25 …suite.addTest("Verify setting a range of bits updates the bit vector correctly.", BitVector_setBit… 30 …suite.addTest("Verify setting a large range of bits updates the bit vector correctly.", BitVector_… 31 …suite.addTest("Verify setting a range of bits with an initial offset updates the bit vector correc… 39 * @tc.desc : Verify setting a range of bits to 0 and 1 updates the bit vector correctly. 52 assertEQ(bitVector[1], 0, "Bit at index 1 should be 0"); 53 assertEQ(bitVector[2], 0, "Bit at index 2 should be 0"); 54 assertEQ(bitVector[3], 0, "Bit at index 3 should be 0"); 56 assertEQ(bitVector[1], 1, "Bit at index 1 should be 1"); 57 assertEQ(bitVector[2], 1, "Bit at index 2 should be 1"); [all …]
D	flipBitsByRangeTests.ets	7 * http://www.apache.org/licenses/LICENSE-2.0 29 …suite.addTest("Test flipBitsByRange with non-integer fromIndex to verify it throws appropriate err… 30 …suite.addTest("Test flipBitsByRange on a 64-bit vector to verify it correctly flips the first half… 31 …suite.addTest("Test flipBitsByRange on a bit vector with initial capacity to verify correct flippi… 52 assertEQ(bitVector[0], 0, "Bit at index 0 should be flipped to 0"); 53 assertEQ(bitVector[1], 0, "Bit at index 1 should be flipped to 0"); 54 assertEQ(bitVector[2], 1, "Bit at index 2 should be flipped to 1"); 55 assertEQ(bitVector[3], 0, "Bit at index 3 should be flipped to 0"); 79 …sage === `The value of "toIndex" is out of range. It must be >= 0 && <= 8. Received value is: -3`); 82 bitVector.flipBitsByRange(8, -3); [all …]
D	getBitCountByRangeTests.ets	7 * http://www.apache.org/licenses/LICENSE-2.0 25 …suite.addTest("Counts the occurrences of a bit element within a valid range.", BitVector_getBitCou… 27 …suite.addTest("Throws an error for non-integer 'fromIndex'.", BitVector_getBitCountByRange_Func_00… 30 …suite.addTest("Counts the occurrences of a bit element in a large range.", BitVector_getBitCountBy… 31 …suite.addTest("Counts the occurrences of a bit element with an initial length.", BitVector_getBitC… 39 * @tc.desc : Counts the occurrences of a bit element within a valid range in a bit vector. 51 …ssertEQ(bitVector.getBitCountByRange(0, 0, 5), 3, "BitVector should contain 3 zeros in range 0-5"); 52 …assertEQ(bitVector.getBitCountByRange(1, 0, 5), 2, "BitVector should contain 2 ones in range 0-5"); 76 …sage === `The value of "toIndex" is out of range. It must be >= 0 && <= 8. Received value is: -3`); 78 expectThrow(() => { bitVector.getBitCountByRange(0, 8, -3); }, exceptionCheck); [all …]
/arkcompiler/ets_runtime/ecmascript/snapshot/mem/
D	encode_bit.h	`7 * http://www.apache.org/licenses/LICENSE-2.0 29 * 16bit 8bit 1bit 1bit 1bit 8bit 1bit 18bit 10bit 44 // encode bit 48 static constexpr int OBJECT_TYPE_BIT_NUMBER = 8; // js_type 52 static constexpr int UNUSED_BIT_NUMBER = 6; // unused bit number`
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/
D	x64_fp_simd_regs.def	`7 * http://www.apache.org/licenses/LICENSE-2.0 17 * - %xmm0–%xmm1 used to pass and return floating point arguments 18 - %xmm2–%xmm7 used to pass floating point arguments 23 …* ID, prefixes: 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, canBeAssigned, isCalleeSave, isParam, isSp… 34 FP_SIMD_REG(8 , "B", "H", "S", "D", "Q", true, false, false, true, false)`
D	x64_int_regs.def	7 * http://www.apache.org/licenses/LICENSE-2.0 17 * Registers in x86-64 19 * - caller-save registers: %rax, %rcx, %rdx, %rdi, %rsi, %rsp, and %r8-r11 20 * - callee-saved registers: %r12, %r13, %r14, %r15, %rbx, %rsp, %rbp. 21 * - In contrast to the Intel386 ABI, %rdi, and %rsi in x86-64 belong to the called function, not 22 * the caller. So, It's caller-save registers 23 …* - User-level applications use as integer registers for passing the sequence %rdi, %rsi, %rdx, %r… 25 * - the sequence %rax, %rdx is used to return INTEGER, 26 * - rdx is used to pass 3rd argument to functions; 2nd return register 27 * - %r11 is neither required to be preserved, nor is it used to pass arguments [all …]
/arkcompiler/ets_runtime/ecmascript/
D	property_attributes.h	`7 * http://www.apache.org/licenses/LICENSE-2.0 66 * Common \| WritableField (bit 1) 67 * \| EnumerableField (bit 2) 68 * \| ConfigurableField (bit 3) 69 * \| IsAccessorField (bit 4) 70 * \| IsInlinedPropsField(bit 5) 71 * \| RepresentationField(bit 6...7) 72 * -------------------------------- 73 * Fast \| OffsetField(bit 8...17) 74 * \| TrackTypeField(bit 18...20) [all …]`
/arkcompiler/runtime_core/static_core/runtime/bridge/arch/x86/
D	compiled_code_to_interpreter_bridge_x86.S	`2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd. 7 * http://www.apache.org/licenses/LICENSE-2.0 32 // %esp % 16 == 12 here (-4 == 12 (mod 16)) 62 // %esp % 16 == 8 here 65 leal -8(%ebp), %ecx // prev* 69 // %esp should be 16-byte aligned here 71 addl $8, %esp // cleanup 76 …// %eax - SHORTY_PTR_REG, %edx - SHORTY_REG, %ecx - shorty value, %edi - iframe.vregs_ + num_vregs… 77 // %esi - args, (%esp) - iframe* 84 leal 8(%ebp), %esi // args [all …]`
D	interpreter_to_compiled_code_bridge_x86.S	`2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd. 7 * http://www.apache.org/licenses/LICENSE-2.0 27 cmpl $(SHORTY_NUM_64BIT_TYPES - 1), %ecx 30 // it is a 32bit value 36 // it is a 64bit value 41 addl $8, \stack_ptr 51 movl 8(\arg_ptr), \tmp1 53 movl \tmp1, 8(\stack_ptr) 62 // %eax - SHORTY_PTR_REG 63 // %edx - SHORTY_REG [all …]`
/arkcompiler/runtime_core/static_core/plugins/ets/tests/checked/
D	ets_static_lookup_8bit.pa	6 # http://www.apache.org/licenses/LICENSE-2.0 14 #! CHECKER Static lookup for 8-bit StObjByName JIT 15 #! RUN force_jit: true, options: "--compiler-regex='.test_store.'", entry: "_GLOBAL::tes… 24 #! CHECKER Static lookup for 8-bit StObjByName AOT 26 #! RUN_PAOC options: "--compiler-regex='.test_store.'" 36 #! CHECKER Static lookup for 8-bit LdObjByName JIT 37 #! RUN force_jit: true, options: "--compiler-regex='.test_load.'", entry: "_GLOBAL::test… 46 #! CHECKER Static lookup for 8-bit LdObjByName AOT 48 #! RUN_PAOC options: "--compiler-regex='.test_load.'" 68 .record $NamedAccessMeta-i8 { [all …]
/arkcompiler/ets_runtime/ecmascript/base/
D	math_helper.h	2 * Copyright (c) 2021-2022 Huawei Device Co., Ltd. 7 * http://www.apache.org/licenses/LICENSE-2.0 24 #define panda_bit_utils_ctz __builtin_ctz // NOLINT(cppcoreguidelines-macro-usage) 25 #define panda_bit_utils_ctzll __builtin_ctzll // NOLINT(cppcoreguidelines-macro-usage) 55 … // -0.0(double) is the special case for std::atanh() function compiled in linux for windows. in Atanh() 56 return -0.0; in Atanh() 66 // Ensure the size of the integer is no more than 8 bytes (64 bits). in WhichPowerOfTwo() 67 static_assert(sizeof(T) <= 8); in WhichPowerOfTwo() 68 // Use __builtin_ctzll for 8 bytes (64 bits) and __builtin_ctz for 32-bit integers. in WhichPowerOfTwo() 69 …return sizeof(T) == 8 ? __builtin_ctzll(static_cast<uint64_t>(value)) : __builtin_ctz(static_cast<… in WhichPowerOfTwo() [all …]
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/assembler/
D	operand.h	7 * http://www.apache.org/licenses/LICENSE-2.0 28 The high 8 bits is register's size. 30 …The fifth bit from right to left is used to identity register rip, the bit equals 1 represents the… 31 …The sixth bit from right to left is used to identity float register, the bit equals 1 represents t… 32 The eighth bit from right to left is used to determine whether 33 …it is the high 8-bit register or the lower 8-bit register, the bit equals 1 represents the lower 8… 35 +-----------------------------------+-----------+-------+---------+-------+-------------------+ 36 \| 15 14 13 12 11 10 9 8 \| 7 \| 6 \| 5 \| 4 \| 3 2 1 0 \| 37 +-----------------------------------+-----------+-------+---------+-------+-------------------+ 38 \| Reg's size in bits \| H/L8-reg \| unuse \| IsFloat \| IsRIP \| Reg's id \| [all …]
/arkcompiler/ets_frontend/es2panda/util/
D	base64.cpp	7 * http://www.apache.org/licenses/LICENSE-2.0 28 // 2: the index do not exceed the range of encodedRes and form a complete four-character block in Base64Encode() 29 …for (size_t i = 0, j = 0; i < encodedRes.length() - 2; i += TRANSFORMED_CHAR_NUM, j += TO_TRANSFOR… in Base64Encode() 30 // convert three 8bit into four 6bit; then add two 0 bit in each 6 bit in Base64Encode() 46 encodedRes[encodedRes.length() - 2] = '='; in Base64Encode() 47 encodedRes[encodedRes.length() - 1] = '='; in Base64Encode() 51 encodedRes[encodedRes.length() - 1] = '='; in Base64Encode() 62 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, in Base64Decode() 63 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, in Base64Decode() 64 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, in Base64Decode() [all …]
/arkcompiler/runtime_core/static_core/docs/
D	code_metainfo.md	`5 Metainfo is an information that aims to provide reg-to-stack mapping for virtual registers. It is n… 14 +-------------+ 16 \| +-------------------+ 20 +-------------+-------------------+ 21 \| \| <-- Method::CompiledCodeEntrypoint 24 +-------------+-----------------+ 26 \| \|-----------------+----------------------+ 31 \| \| Bit Tables \| Method indexes \| 37 \|-------------+-----------------+----------------------+ 40 ## Bit table [all …]`
/arkcompiler/runtime_core/docs/
D	code_metainfo.md	`5 Metainfo is an information that aims to provide reg-to-stack mapping for virtual registers. It is n… 14 +-------------+ 16 \| +-------------------+ 20 +-------------+-------------------+ 21 \| \| <-- Method::CompiledCodeEntrypoint 24 +-------------+-----------------+ 26 \| \|-----------------+----------------------+ 31 \| \| Bit Tables \| Method indexes \| 37 \|-------------+-----------------+----------------------+ 40 ## Bit table [all …]`
/arkcompiler/runtime_core/static_core/runtime/bridge/arch/arm/
D	interpreter_to_compiled_code_bridge_arm.S	`2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd. 7 * http://www.apache.org/licenses/LICENSE-2.0 28 cmp r2, #(SHORTY_NUM_64BIT_TYPES - 1) 30 // it is a 32bit value 34 1: // it is a 64bit value 36 add \stack_ptr, \stack_ptr, #7 // round the address up to 8 byte boundary 42 add \stack_ptr, \stack_ptr, #7 // round the address up to 8 byte boundary 67 bic sp, sp, #7 // round downd sp to 8byte boundary 72 // r0 - SHORTY_PTR_REG 73 // r1 - SHORTY_REG [all …]`
D	compiled_code_to_interpreter_bridge_arm.S	`2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd. 7 * http://www.apache.org/licenses/LICENSE-2.0 36 // store r0-r3 before the frame to make arg array continuos with stack args 37 push {r0-r3} 43 CFI_ADJUST_CFA_OFFSET(8) 46 CFI_ADJUST_CFA_OFFSET(8) 49 CFI_ADJUST_CFA_OFFSET(-4) 57 push {r4 - r10} 58 CFI_REL_OFFSET(r10, -(2 * 4)) 59 CFI_REL_OFFSET(r9, -(3 * 4)) [all …]`
/arkcompiler/runtime_core/static_core/libpandabase/utils/
D	bit_field.h	2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd. 7 * http://www.apache.org/licenses/LICENSE-2.0 29 static constexpr unsigned BITS_PER_BYTE = 8; 52 * Make BitField type that follows right after current bit range. 67 * Make Flag field that follows right after current bit range. 74 * Return maximum value that fits bit range [START_BIT : START_BIT+END_BIT] 78 return (1LLU << BITS_NUM) - 1; in MaxValue() 82 * Return mask of bit range, f.e. 0b1110 for BitField<T, 1, 3> 90 * Check if given value fits into the bit field 98 * Set 'value' to current bit range [START_BIT : START_BIT+END_BIT] within the 'stor' parameter. [all …]
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/aarch64/
D	aarch64_fp_simd_regs.def	`7 * http://www.apache.org/licenses/LICENSE-2.0 22 * ID, 128 bit vector prefix, followed by scalar prefixes 23 …* scalar prefixes: 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, canBeAssigned, isCalleeSave, isParam, i… 24 * (e.g., we use D0 when V0 contains a 64-bit scalar FP number (aka, double)) 34 FP_SIMD_REG(8 , "V", "B", "H", "S", "D", "Q", true, true, false, false, false)`

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