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/kernel/linux/linux-5.10/drivers/gpu/ipu-v3/
Dipu-cpmem.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include "ipu-prv.h"
30 #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
93 ipu_get_cpmem(struct ipuv3_channel *ch) in ipu_get_cpmem() argument
95 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; in ipu_get_cpmem()
97 return cpmem->base + ch->num; in ipu_get_cpmem()
100 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) in ipu_ch_param_write_field() argument
102 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); in ipu_ch_param_write_field()
103 u32 bit = (wbs >> 8) % 160; in ipu_ch_param_write_field()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/ipu-v3/
Dipu-cpmem.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include "ipu-prv.h"
30 #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
93 ipu_get_cpmem(struct ipuv3_channel *ch) in ipu_get_cpmem() argument
95 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; in ipu_get_cpmem()
97 return cpmem->base + ch->num; in ipu_get_cpmem()
100 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) in ipu_ch_param_write_field() argument
102 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); in ipu_ch_param_write_field()
103 u32 bit = (wbs >> 8) % 160; in ipu_ch_param_write_field()
[all …]
/kernel/linux/linux-5.10/drivers/scsi/
Dch.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * (c) 1996-2003 Gerd Knorr <kraxel@bytesex.org>
38 #define CH_TYPES 8
71 static int dt_id[CH_DT_MAX] = { [ 0 ... (CH_DT_MAX-1) ] = -1 };
76 /* tell the driver about vendor-specific slots */
77 static int vendor_firsts[CH_TYPES-4];
78 static int vendor_counts[CH_TYPES-4];
82 static const char * vendor_labels[CH_TYPES-4] = {
87 #define ch_printk(prefix, ch, fmt, a...) \ argument
88 sdev_prefix_printk(prefix, (ch)->device, (ch)->name, fmt, ##a)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/imx/dcss/
Ddcss-dpr.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "dcss-dev.h"
36 #define PIX_SIZE_POS 8
37 #define PIX_SIZE_MASK GENMASK(9, 8)
118 struct dcss_dpr_ch ch[3]; member
121 static void dcss_dpr_write(struct dcss_dpr_ch *ch, u32 val, u32 ofs) in dcss_dpr_write() argument
123 struct dcss_dpr *dpr = ch->dpr; in dcss_dpr_write()
125 dcss_ctxld_write(dpr->ctxld, dpr->ctx_id, val, ch->base_ofs + ofs); in dcss_dpr_write()
130 struct dcss_dpr_ch *ch; in dcss_dpr_ch_init_all() local
134 ch = &dpr->ch[i]; in dcss_dpr_ch_init_all()
[all …]
Ddcss-scaler.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "dcss-dev.h"
16 #define SCALE2MEM_EN BIT(8)
33 #define A2R10G10B10_FORMAT_POS 8
34 #define A2R10G10B10_FORMAT_MASK GENMASK(11, 8)
90 struct dcss_scaler_ch ch[3]; member
103 #define PSC_PHASE_MASK (PSC_NUM_PHASES - 1)
105 #define PSC_Q_ROUND_OFFSET (1 << (PSC_Q_FRACTION - 1))
108 * mult_q() - Performs fixed-point multiplication.
124 * div_q() - Performs fixed-point division.
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/imx/dcss/
Ddcss-dpr.c1 // SPDX-License-Identifier: GPL-2.0
9 #include "dcss-dev.h"
36 #define PIX_SIZE_POS 8
37 #define PIX_SIZE_MASK GENMASK(9, 8)
118 struct dcss_dpr_ch ch[3]; member
121 static void dcss_dpr_write(struct dcss_dpr_ch *ch, u32 val, u32 ofs) in dcss_dpr_write() argument
123 struct dcss_dpr *dpr = ch->dpr; in dcss_dpr_write()
125 dcss_ctxld_write(dpr->ctxld, dpr->ctx_id, val, ch->base_ofs + ofs); in dcss_dpr_write()
130 struct dcss_dpr_ch *ch; in dcss_dpr_ch_init_all() local
134 ch = &dpr->ch[i]; in dcss_dpr_ch_init_all()
[all …]
Ddcss-scaler.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "dcss-dev.h"
16 #define SCALE2MEM_EN BIT(8)
33 #define A2R10G10B10_FORMAT_POS 8
34 #define A2R10G10B10_FORMAT_MASK GENMASK(11, 8)
88 struct dcss_scaler_ch ch[3]; member
101 #define PSC_PHASE_MASK (PSC_NUM_PHASES - 1)
103 #define PSC_Q_ROUND_OFFSET (1 << (PSC_Q_FRACTION - 1))
106 * mult_q() - Performs fixed-point multiplication.
122 * div_q() - Performs fixed-point division.
[all …]
/kernel/linux/linux-6.6/drivers/scsi/
Dch.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * (c) 1996-2003 Gerd Knorr <kraxel@bytesex.org>
38 #define CH_TYPES 8
71 static int dt_id[CH_DT_MAX] = { [ 0 ... (CH_DT_MAX-1) ] = -1 };
76 /* tell the driver about vendor-specific slots */
77 static int vendor_firsts[CH_TYPES-4];
78 static int vendor_counts[CH_TYPES-4];
82 static const char * vendor_labels[CH_TYPES-4] = {
87 #define ch_printk(prefix, ch, fmt, a...) \ argument
88 sdev_prefix_printk(prefix, (ch)->device, (ch)->name, fmt, ##a)
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/
Dsh_mobile_lcdcfb.c16 #include <linux/dma-mapping.h>
36 /* ----------------------------------------------------------------------------
42 #define LDBCR_UPF(n) (1 << ((n) + 8))
66 #define LDBBSIFR_SWPB (1 << 8)
95 #define LDBBSAYR_FG1G_MASK (0xff << 8)
96 #define LDBBSAYR_FG1G_SHIFT 8
104 #define LDBBSACR_FG2G_MASK (0xff << 8)
105 #define LDBBSACR_FG2G_SHIFT 8
113 #define LDBBSAAR_GY_MASK (0xff << 8)
114 #define LDBBSAAR_GY_SHIFT 8
[all …]
/kernel/linux/linux-6.6/drivers/video/fbdev/
Dsh_mobile_lcdcfb.c16 #include <linux/dma-mapping.h>
35 /* ----------------------------------------------------------------------------
41 #define LDBCR_UPF(n) (1 << ((n) + 8))
65 #define LDBBSIFR_SWPB (1 << 8)
94 #define LDBBSAYR_FG1G_MASK (0xff << 8)
95 #define LDBBSAYR_FG1G_SHIFT 8
103 #define LDBBSACR_FG2G_MASK (0xff << 8)
104 #define LDBBSACR_FG2G_SHIFT 8
112 #define LDBBSAAR_GY_MASK (0xff << 8)
113 #define LDBBSAAR_GY_SHIFT 8
[all …]
/kernel/linux/linux-5.10/arch/x86/crypto/
Dsha512-avx2-asm.S2 # Implement fast SHA-512 with AVX2 instructions. (x86_64)
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
100 XFER_SIZE = 4*8
101 SRND_SIZE = 1*8
102 INP_SIZE = 1*8
103 INPEND_SIZE = 1*8
104 CTX_SIZE = 1*8
[all …]
/kernel/linux/linux-5.10/sound/pci/emu10k1/
Demu10k1_callback.c1 // SPDX-License-Identifier: GPL-2.0-or-later
42 * macro evaluates its args more than once, so changed to upper-case.
67 emux->ops = emu10k1_ops; in snd_emu10k1_ops_setup()
86 emu = hw->synth; in snd_emu10k1_synth_get_voice()
91 int ch; in snd_emu10k1_synth_get_voice() local
92 vp = &emu->voices[best[i].voice]; in snd_emu10k1_synth_get_voice()
93 if ((ch = vp->ch) < 0) { in snd_emu10k1_synth_get_voice()
95 dev_warn(emu->card->dev, in snd_emu10k1_synth_get_voice()
96 "synth_get_voice: ch < 0 (%d) ??", i); in snd_emu10k1_synth_get_voice()
100 vp->emu->num_voices--; in snd_emu10k1_synth_get_voice()
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/
Drz-mtu3.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
48 #define RZ_MTU3_TBTM 8 /* Timer buffer operation transfer mode register */
50 /* 8-bit MTU5 register offset macros */
57 #define RZ_MTU3_TCR2V 8 /* Timer control register 2V */
63 /* 16-bit register offset macros of MTU3 channels except MTU5 */
73 #define RZ_MTU3_TADCORA 8 /* cycle set register A */
78 /* 16-bit MTU5 register offset macros */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/aspeed/
Daspeed-bmc-amd-daytonax.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "amd,daytonax-bmc", "aspeed,ast2500";
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
24 compatible = "shared-dma-pool";
[all …]
/kernel/linux/linux-6.6/arch/x86/crypto/
Dsha512-avx2-asm.S2 # Implement fast SHA-512 with AVX2 instructions. (x86_64)
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
101 XFER_SIZE = 4*8
102 SRND_SIZE = 1*8
103 INP_SIZE = 1*8
104 INPEND_SIZE = 1*8
105 CTX_SIZE = 1*8
[all …]
/kernel/linux/linux-6.6/arch/mips/lantiq/xway/
Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
36 #define DMA_TX BIT(8) /* TX channel direction */
46 #define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */
49 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
61 ltq_dma_enable_irq(struct ltq_dma_channel *ch) in ltq_dma_enable_irq() argument
66 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_enable_irq()
67 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); in ltq_dma_enable_irq()
73 ltq_dma_disable_irq(struct ltq_dma_channel *ch) in ltq_dma_disable_irq() argument
78 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_disable_irq()
[all …]
/kernel/linux/linux-5.10/drivers/clk/uniphier/
Dclk-uniphier-mio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "clk-uniphier.h"
12 UNIPHIER_CLK_FACTOR("sd-44m", -1, "sd-133m", 1, 3), \
13 UNIPHIER_CLK_FACTOR("sd-33m", -1, "sd-200m", 1, 6), \
14 UNIPHIER_CLK_FACTOR("sd-50m", -1, "sd-200m", 1, 4), \
15 UNIPHIER_CLK_FACTOR("sd-67m", -1, "sd-200m", 1, 3), \
16 UNIPHIER_CLK_FACTOR("sd-100m", -1, "sd-200m", 1, 2), \
17 UNIPHIER_CLK_FACTOR("sd-40m", -1, "sd-200m", 1, 5), \
18 UNIPHIER_CLK_FACTOR("sd-25m", -1, "sd-200m", 1, 8), \
19 UNIPHIER_CLK_FACTOR("sd-22m", -1, "sd-133m", 1, 6)
[all …]
/kernel/linux/linux-6.6/drivers/clk/uniphier/
Dclk-uniphier-mio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "clk-uniphier.h"
12 UNIPHIER_CLK_FACTOR("sd-44m", -1, "sd-133m", 1, 3), \
13 UNIPHIER_CLK_FACTOR("sd-33m", -1, "sd-200m", 1, 6), \
14 UNIPHIER_CLK_FACTOR("sd-50m", -1, "sd-200m", 1, 4), \
15 UNIPHIER_CLK_FACTOR("sd-67m", -1, "sd-200m", 1, 3), \
16 UNIPHIER_CLK_FACTOR("sd-100m", -1, "sd-200m", 1, 2), \
17 UNIPHIER_CLK_FACTOR("sd-40m", -1, "sd-200m", 1, 5), \
18 UNIPHIER_CLK_FACTOR("sd-25m", -1, "sd-200m", 1, 8), \
19 UNIPHIER_CLK_FACTOR("sd-22m", -1, "sd-133m", 1, 6)
[all …]
/kernel/linux/linux-5.10/lib/
Dhexdump.c1 // SPDX-License-Identifier: GPL-2.0-only
20 * hex_to_bin - convert a hex digit to its real value
21 * @ch: ascii character represents hex digit
23 * hex_to_bin() converts one hex digit to its actual value or -1 in case of bad
30 * (ch - '9' - 1) is negative if ch <= '9'
31 * ('0' - 1 - ch) is negative if ch >= '0'
32 * we "and" these two values, so the result is negative if ch is in the range
34 * we are only interested in the sign, so we do a shift ">> 8"; note that right
35 * shift of a negative value is implementation-defined, so we cast the
36 * value to (unsigned) before the shift --- we have 0xffffff if ch is in
[all …]
/kernel/linux/linux-6.6/lib/
Dhexdump.c1 // SPDX-License-Identifier: GPL-2.0-only
20 * hex_to_bin - convert a hex digit to its real value
21 * @ch: ascii character represents hex digit
23 * hex_to_bin() converts one hex digit to its actual value or -1 in case of bad
30 * (ch - '9' - 1) is negative if ch <= '9'
31 * ('0' - 1 - ch) is negative if ch >= '0'
32 * we "and" these two values, so the result is negative if ch is in the range
34 * we are only interested in the sign, so we do a shift ">> 8"; note that right
35 * shift of a negative value is implementation-defined, so we cast the
36 * value to (unsigned) before the shift --- we have 0xffffff if ch is in
[all …]
/kernel/linux/linux-6.6/drivers/gpio/
Dgpio-ml-ioh.c1 // SPDX-License-Identifier: GPL-2.0-only
38 struct ioh_reg_comn regs[8];
46 * struct ioh_gpio_reg_data - The register store data.
66 * struct ioh_gpio - GPIO private data structure.
74 * @ch: Indicate GPIO channel
85 int ch; member
98 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_set()
99 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_set()
105 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_set()
106 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_set()
[all …]
/kernel/linux/linux-6.6/drivers/clk/berlin/
Dberlin2-avpll.c1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 #include <linux/clk-provider.h>
15 #include "berlin2-avpll.h"
19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
29 #define NUM_CHANNELS 8
46 #define VCO_REG0V9_SEL_SHIFT 8
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
130 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
[all …]
/kernel/linux/linux-5.10/drivers/clk/berlin/
Dberlin2-avpll.c1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 #include <linux/clk-provider.h>
15 #include "berlin2-avpll.h"
19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
29 #define NUM_CHANNELS 8
46 #define VCO_REG0V9_SEL_SHIFT 8
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
130 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
[all …]
/kernel/linux/linux-6.6/sound/soc/fsl/
Dfsl_micfil.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
38 /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
53 #define MICFIL_CTRL1_CHEN(ch) BIT(ch) argument
55 /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
68 /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
72 #define MICFIL_STAT_CHXF(ch) BIT(ch) argument
74 /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
77 /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
78 #define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch) argument
79 #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8) argument
[all …]
/kernel/linux/linux-6.6/drivers/tty/serial/jsm/
Djsm_neo.c1 // SPDX-License-Identifier: GPL-2.0+
20 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
35 static void neo_set_cts_flow_control(struct jsm_channel *ch) in neo_set_cts_flow_control() argument
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
[all …]

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