| /kernel/linux/linux-6.6/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos-arm64.c | 1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
44 * Bank type for non-alive type. Bit fields:
64 /* pin banks of exynos5433 pin-controller - ALIVE */
67 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
68 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
69 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
70 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
[all …]
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| D | pinctrl-exynos-arm.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
62 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
64 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
66 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
70 return ERR_PTR(-ENODEV); in s5pv210_retention_init()
77 return ERR_PTR(-EINVAL); in s5pv210_retention_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos-arm.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
62 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
64 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
66 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
70 return ERR_PTR(-ENODEV); in s5pv210_retention_init()
77 return ERR_PTR(-EINVAL); in s5pv210_retention_init()
[all …]
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| D | pinctrl-exynos-arm64.c | 1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
46 /* pin banks of exynos5433 pin-controller - ALIVE */
49 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
50 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
51 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
52 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
53 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-mt7622.txt | 4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 "mediatek,mt7629-pinctrl" for MT7629 SoC
7 - reg: offset and length of the pinctrl space
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells: Should be two. The first cell is the pin number and the
14 - interrupt-controller : Marks the device node as an interrupt controller
16 If the property interrupt-controller is defined, following property is required
17 - reg-names: A string describing the "reg" entries. Must contain "eint".
18 - interrupts : The interrupt output from the controller.
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| D | fsl,mxs-pinctrl.txt | 1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
20 information about pull-up. For this reason, even seemingly boolean values are
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/ |
| D | sama5d3_lcd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,sama5d3-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
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| D | at91sam9x5_lcd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,at91sam9x5-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | sama5d3_lcd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * sama5d3_lcd.dtsi - Device Tree Include file for SAMA5D3 SoC with
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,sama5d3-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
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| D | at91sam9x5_lcd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "atmel,at91sam9x5-hlcdc";
20 clock-names = "periph_clk","sys_clk", "slow_clk";
23 hlcdc-display-controller {
24 compatible = "atmel,hlcdc-display-controller";
25 #address-cells = <1>;
26 #size-cells = <0>;
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| D | exynos3250-artik5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
21 stdout-path = &serial_2;
30 compatible = "samsung,secure-firmware";
34 thermal-zones {
35 cpu_thermal: cpu-thermal {
36 cooling-maps {
39 cooling-device = <&cpu0 5 5>,
[all …]
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| D | s3c2416-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/pinctrl/samsung.h>
12 * Pin banks
16 gpio-controller;
17 #gpio-cells = <2>;
21 gpio-controller;
22 #gpio-cells = <2>;
26 gpio-controller;
27 #gpio-cells = <2>;
31 gpio-controller;
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| D | exynos4210-i9100.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-event-codes.h>
19 model = "Samsung Galaxy S2 (GT-I9100)";
28 stdout-path = "serial2:115200n8";
31 vemmc_reg: regulator-0 {
32 compatible = "regulator-fixed";
[all …]
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| /kernel/linux/linux-6.6/drivers/pinctrl/renesas/ |
| D | pinctrl-rza1.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
11 * This includes SoCs which are sub- or super- sets of this particular line,
22 #include <linux/pinctrl/pinconf-generic.h>
34 #define DRIVER_NAME "pinctrl-rza1"
56 * Use 16 lower bits [15:0] for pin identifier
57 * Use 16 higher bits [31:16] for pin mux function
69 /* Pin mux flags */
74 /* ----------------------------------------------------------------------------
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/renesas/ |
| D | pinctrl-rza1.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
11 * This includes SoCs which are sub- or super- sets of this particular line,
24 #include <linux/pinctrl/pinconf-generic.h>
34 #define DRIVER_NAME "pinctrl-rza1"
56 * Use 16 lower bits [15:0] for pin identifier
57 * Use 16 higher bits [31:16] for pin mux function
69 /* Pin mux flags */
74 /* ----------------------------------------------------------------------------
[all …]
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| /kernel/linux/linux-6.6/drivers/gpio/ |
| D | gpio-zynqmp-modepin.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the ps-mode pin configuration.
16 #include <linux/firmware/xlnx-zynqmp.h>
18 /* 4-bit boot mode pins */
22 * modepin_gpio_get_value - Get the state of the specified pin of GPIO device
24 * @pin: gpio pin number within the device
26 * This function reads the state of the specified pin of the GPIO device.
28 * Return: 0 if the pin is low, 1 if pin is high, -EINVAL wrong pin configured
31 static int modepin_gpio_get_value(struct gpio_chip *chip, unsigned int pin) in modepin_gpio_get_value() argument
40 /* When [0:3] corresponding bit is set, then read output bit [8:11], in modepin_gpio_get_value()
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/ |
| D | exynos5433-tm2-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h>
48 stdout-path = &serial_1;
56 gpio-keys {
57 compatible = "gpio-keys";
[all …]
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| /kernel/linux/linux-6.6/Documentation/driver-api/ |
| D | pin-control.rst | 2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
[all …]
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| /kernel/linux/linux-5.10/Documentation/driver-api/ |
| D | pinctl.rst | 2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up/down, open drain,
17 Top-level interface
20 Definition of PIN CONTROLLER:
22 - A pin controller is a piece of hardware, usually a set of registers, that
26 Definition of PIN:
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,mxs-pinctrl.txt | 1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
20 information about pull-up. For this reason, even seemingly boolean values are
[all …]
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| D | sunplus,sp7021-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus SP7021 Pin Controller
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
23 (1) function-group pins:
[all …]
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| /kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/ |
| D | global2_scratch.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
22 reg << 8); in mv88e6xxx_g2_scratch_read()
38 u16 value = (reg << 8) | data; in mv88e6xxx_g2_scratch_write()
45 * mv88e6xxx_g2_scratch_gpio_get_bit - get a bit
55 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_get_bit()
70 * mv88e6xxx_g2_scratch_gpio_set_bit - set (or clear) a bit
82 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_set_bit()
100 * mv88e6352_g2_scratch_gpio_get_data - get data on gpio pin
102 * @pin: gpio index
107 unsigned int pin) in mv88e6352_g2_scratch_gpio_get_data() argument
[all …]
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| /kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/ |
| D | global2_scratch.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
22 reg << 8); in mv88e6xxx_g2_scratch_read()
38 u16 value = (reg << 8) | data; in mv88e6xxx_g2_scratch_write()
45 * mv88e6xxx_g2_scratch_get_bit - get a bit
55 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_get_bit()
70 * mv88e6xxx_g2_scratch_set_bit - set (or clear) a bit
82 int reg = base_reg + (offset / 8); in mv88e6xxx_g2_scratch_set_bit()
100 * mv88e6352_g2_scratch_gpio_get_data - get data on gpio pin
102 * @pin: gpio index
107 unsigned int pin) in mv88e6352_g2_scratch_gpio_get_data() argument
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/samsung/ |
| D | exynos3250-artik5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
26 stdout-path = &serial_2;
35 compatible = "samsung,secure-firmware";
39 thermal-zones {
40 cpu_thermal: cpu-thermal {
41 cooling-maps {
44 cooling-device = <&cpu0 5 5>,
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| D | s3c64xx-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
12 #include "s3c64xx-pinctrl.h"
16 * Pin banks
19 gpa: gpa-gpio-bank {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
[all …]
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