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/kernel/linux/linux-5.10/arch/x86/kernel/cpu/
Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
48 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
49 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
50 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
51 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
52 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
53 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
[all …]
Dintel.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <asm/intel-family.h>
61 * Processors which have self-snooping capability can handle conflicting
69 switch (c->x86_model) { in check_memory_type_self_snoop_errata()
101 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
103 switch (c->x86_model) { in probe_xeon_phi_r3mwait()
125 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
126 * - https://kb.vmware.com/s/article/52345
127 * - Microcode revisions observed in the wild
128 * - Release note from 20180108 microcode release
[all …]
/kernel/linux/linux-6.6/arch/x86/kernel/cpu/
Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
63 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
65 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
66 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
67 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
68 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
[all …]
Dintel.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <asm/intel-family.h>
67 * Processors which have self-snooping capability can handle conflicting
75 switch (c->x86_vfm) { in check_memory_type_self_snoop_errata()
107 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
109 switch (c->x86_vfm) { in probe_xeon_phi_r3mwait()
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
[all …]
/kernel/linux/linux-5.10/arch/arc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
25 * -local_flush_tlb_range( ):
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/kernel/linux/linux-6.6/arch/mips/kernel/
Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
87 #define BRCM_ZSC_RBUS_ADDR_MAPPING_REG2 8 << 3
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
137 /* sets per way = (64<<IS) */
146 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
164 /* v0 now have sets per way, multiply it by line size now
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/kernel/linux/linux-5.10/arch/mips/kernel/
Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
87 #define BRCM_ZSC_RBUS_ADDR_MAPPING_REG2 8 << 3
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
137 /* sets per way = (64<<IS) */
146 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
164 /* v0 now have sets per way, multiply it by line size now
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/kernel/linux/linux-5.10/arch/arm/mm/
Dcache-xsc3l2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
17 #define CACHE_WAY_PER_SET 8
19 #define CACHE_WAY_SIZE(l2ctype) (8192 << (((l2ctype) >> 8) & 0xf))
44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
61 if (va != -1) in l2_unmap_va()
70 unsigned long pa_offset = pa << (32 - PAGE_SHIFT); in l2_map_va()
71 if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { in l2_map_va()
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/kernel/linux/linux-6.6/arch/arm/mm/
Dcache-xsc3l2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
17 #define CACHE_WAY_PER_SET 8
19 #define CACHE_WAY_SIZE(l2ctype) (8192 << (((l2ctype) >> 8) & 0xf))
44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
61 if (va != -1) in l2_unmap_va()
70 unsigned long pa_offset = pa << (32 - PAGE_SHIFT); in l2_map_va()
71 if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { in l2_map_va()
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/kernel/linux/linux-6.6/arch/openrisc/include/asm/
Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
35 #define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)
49 #define SPR_PCCFGR (SPRGROUP_SYS + 8)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) argument
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/kernel/linux/linux-5.10/arch/openrisc/include/asm/
Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
35 #define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)
49 #define SPR_PCCFGR (SPRGROUP_SYS + 8)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) argument
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/kernel/linux/linux-5.10/Documentation/x86/
Dentry_64.rst1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
28 either way.
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
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/kernel/linux/linux-6.6/Documentation/arch/x86/
Dentry_64.rst1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
28 either way.
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
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/kernel/linux/linux-6.6/Documentation/admin-guide/
Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem OBSOLETE - replaced by /proc/kcore
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
13 8 = /dev/random Nondeterministic random number gen.
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
67 8 = /dev/fd?h1200 5.25" 1200K in a 1200K drive(1)
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/kernel/linux/linux-5.10/Documentation/admin-guide/
Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
13 8 = /dev/random Nondeterministic random number gen.
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
67 8 = /dev/fd?h1200 5.25" 1200K in a 1200K drive(1)
106 3 char Pseudo-TTY slaves
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/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm2836.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "bcm2835-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 local_intc: interrupt-controller@40000000 {
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a7-pmu";
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/kernel/linux/linux-5.10/arch/mips/mm/
Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
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/kernel/linux/linux-6.6/arch/mips/mm/
Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
[all …]
/kernel/linux/linux-6.6/arch/arm/include/asm/
Dv7m.h1 /* SPDX-License-Identifier: GPL-2.0 */
49 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
50 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
62 /* Memory-mapped MPU registers for M-class */
75 #define PMSAv8_RBAR_A(n) (PMSAv8_RBAR + 8*(n))
76 #define PMSAv8_RLAR_A(n) (PMSAv8_RLAR + 8*(n))
81 #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
82 #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
83 #define V7M_SCB_DCIMVAC 0x25c /* D-cache invalidate by MVA to PoC */
84 #define V7M_SCB_DCISW 0x260 /* D-cache invalidate by set-way */
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/kernel/linux/linux-5.10/arch/arm/include/asm/
Dv7m.h1 /* SPDX-License-Identifier: GPL-2.0 */
48 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
49 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
61 /* Memory-mapped MPU registers for M-class */
74 #define PMSAv8_RBAR_A(n) (PMSAv8_RBAR + 8*(n))
75 #define PMSAv8_RLAR_A(n) (PMSAv8_RLAR + 8*(n))
80 #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
81 #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
82 #define V7M_SCB_DCIMVAC 0x25c /* D-cache invalidate by MVA to PoC */
83 #define V7M_SCB_DCISW 0x260 /* D-cache invalidate by set-way */
[all …]
/kernel/linux/linux-6.6/arch/arc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
175 * Flush the entire MM for userland. The fastest way is to move to Next ASID
185 if (atomic_read(&mm->mm_users) == 0) in local_flush_tlb_mm()
189 * - Move to a new ASID, but only if the mm is still wired in in local_flush_tlb_mm()
190 * (Android Binder ended up calling this for vma->mm != tsk->mm, in local_flush_tlb_mm()
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/kernel/linux/linux-5.10/arch/x86/crypto/
Dblowfish-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 .file "blowfish-x86_64-asm.S"
57 * 1-way blowfish
83 movq p+4*(n-1)(CTX), RT0; \
125 round_enc(8);
177 4-way blowfish, four blocks parallel
180 /* F() for 4-way. Slower when used alone/1-way, but faster when used
181 * parallel/4-way (tested on AMD Phenom II & Intel Xeon E7330).
223 movq p+4*((n)-1)(CTX), RKEY; \
228 preload_roundkey_dec(n - 2);
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/kernel/linux/linux-6.6/arch/x86/crypto/
Dblowfish-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 .file "blowfish-x86_64-asm.S"
57 * 1-way blowfish
83 movq p+4*(n-1)(CTX), RT0; \
120 round_enc(8);
166 4-way blowfish, four blocks parallel
169 /* F() for 4-way. Slower when used alone/1-way, but faster when used
170 * parallel/4-way (tested on AMD Phenom II & Intel Xeon E7330).
212 movq p+4*((n)-1)(CTX), RKEY; \
217 preload_roundkey_dec(n - 2);
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/
Dmt7530.h1 /* SPDX-License-Identifier: GPL-2.0-only */
36 #define UNU_FFP(x) (((x) & 0xff) << 8)
88 #define ATC_MAT(x) (((x) & 0xf) << 8)
103 #define MAC_BYTE_2 8
177 #define PORT_RX_MIR BIT(8)
210 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
227 /* Register for port port-and-protocol based vlan 1 control */
242 #define PMCR_BACKPR_EN BIT(8)
313 ((p) - 5) * 0x1000 + (r))
328 #define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
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/kernel/linux/linux-6.6/arch/ia64/lib/
Dstrlen.S1 /* SPDX-License-Identifier: GPL-2.0 */
14 * Copyright (C) 1999, 2001 Hewlett-Packard Co
30 // The goal is to look at the string in chunks of 8 bytes.
32 // string may not be 8-byte aligned. In this case we load the 8byte
36 // latency and do read ahead safely. This way we defer any exception.
55 // - the cmp r0,r0 is used as a fast way to initialize a predicate
59 // - we don't use the epilogue counter to exit the loop but we need to set
62 // - after the loop we must test for Nat values because neither the
68 // - Clearly performance tuning is required.
86 alloc saved_pfs=ar.pfs,11,0,0,8 // rotating must be multiple of 8
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