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/kernel/linux/linux-5.10/drivers/clk/bcm/
Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
49 .channel = BCM_SR_GENPLL0_125M_CLK,
52 .mdiv = REG_VAL(0x18, 0, 9),
55 .channel = BCM_SR_GENPLL0_SCR_CLK,
58 .mdiv = REG_VAL(0x18, 10, 9),
61 .channel = BCM_SR_GENPLL0_250M_CLK,
64 .mdiv = REG_VAL(0x18, 20, 9),
[all …]
Dclk-cygnus.c16 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/bcm-cygnus.h>
24 #include "clk-iproc.h"
55 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
73 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
79 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
85 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
91 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
93 .enable = ENABLE_VAL(0x4, 9, 3, 15),
97 .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
[all …]
/kernel/linux/linux-6.6/drivers/clk/bcm/
Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
49 .channel = BCM_SR_GENPLL0_125M_CLK,
52 .mdiv = REG_VAL(0x18, 0, 9),
55 .channel = BCM_SR_GENPLL0_SCR_CLK,
58 .mdiv = REG_VAL(0x18, 10, 9),
61 .channel = BCM_SR_GENPLL0_250M_CLK,
64 .mdiv = REG_VAL(0x18, 20, 9),
[all …]
Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
63 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
69 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
75 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
81 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
83 .enable = ENABLE_VAL(0x4, 9, 3, 15),
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dnvidia,tegra210-admaif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13 Tx channel and ADMA channel receiving data from AHUB pairs with
14 ADMAIF Rx channel.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
[all …]
Dsnps,designware-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jose Abreu <joabreu@synopsys.com>
15 - items:
16 - const: canaan,k210-i2s
17 - const: snps,designware-i2s
18 - enum:
19 - snps,designware-i2s
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dnvidia,tegra210-admaif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13 Tx channel and ADMA channel receiving data from AHUB pairs with
14 ADMAIF Rx channel.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr-channel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR channel with chip/rank topology description
10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
23 - jedec,lpddr4-channel
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/
Dat91-natte.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-natte.dts - Device Tree include file for the Natte board
11 mux: mux-controller {
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
22 io-channels = <&adc 5>;
23 io-channel-names = "parent";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dat91-natte.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-natte.dts - Device Tree include file for the Natte board
11 mux: mux-controller {
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
22 io-channels = <&adc 5>;
23 io-channel-names = "parent";
[all …]
/kernel/linux/linux-6.6/drivers/hsi/controllers/
Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
72 #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) argument
82 # define SSI_NOTEMPTY(channel) (1 << (channel)) argument
[all …]
/kernel/linux/linux-5.10/drivers/hsi/controllers/
Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
72 #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) argument
82 # define SSI_NOTEMPTY(channel) (1 << (channel)) argument
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/
Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/input/
Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
[all …]
/kernel/linux/linux-5.10/sound/soc/sprd/
Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
57 /* Channel water mark definition */
62 /* DMA channel select definition */
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
80 #define MCDT_CH_FIFO_ADDR_MASK GENMASK(9, 0)
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
128 static void sprd_mcdt_dac_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel, in sprd_mcdt_dac_set_watermark() argument
[all …]
/kernel/linux/linux-6.6/sound/soc/sprd/
Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
57 /* Channel water mark definition */
62 /* DMA channel select definition */
75 /* DMA channel ACK select definition */
78 /* Channel FIFO definition */
80 #define MCDT_CH_FIFO_ADDR_MASK GENMASK(9, 0)
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
128 static void sprd_mcdt_dac_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel, in sprd_mcdt_dac_set_watermark() argument
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/
Dregs-lcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
23 #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
24 #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */
25 #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */
26 #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */
27 #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */
28 #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */
51 #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
52 #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
[all …]
/kernel/linux/linux-5.10/drivers/iio/adc/
Dtwl6030-gpadc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2013 Texas Instruments Inc.
13 * Based on twl4030-madc.c
73 * struct twl6030_chnl_calib - channel calibration
85 * struct twl6030_ideal_code - GPADC calibration parameters
89 * @channel: channel number
96 int channel; member
106 * struct twl6030_gpadc_platform_data - platform specific data
111 * @channel_to_reg: pointer to ADC function to convert channel to
119 int (*start_conversion)(int channel);
[all …]
/kernel/linux/linux-6.6/drivers/iio/adc/
Dtwl6030-gpadc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2013 Texas Instruments Inc.
13 * Based on twl4030-madc.c
73 * struct twl6030_chnl_calib - channel calibration
85 * struct twl6030_ideal_code - GPADC calibration parameters
89 * @channel: channel number
96 int channel; member
106 * struct twl6030_gpadc_platform_data - platform specific data
111 * @channel_to_reg: pointer to ADC function to convert channel to
119 int (*start_conversion)(int channel);
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/
Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/microchip/
Dlan743x_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
64 #define PMT_CTL_RES_CLR_WKP_MASK_ GENMASK(9, 8)
131 #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8)
151 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
152 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
153 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
156 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
157 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
158 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
233 #define MAC_WUCSR_RFE_WAKE_FR_ BIT(9)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/zydas/zd1211rw/
Dzd_rf_uw2453.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
20 /* The 3-wire serial interface provides access to 8 write-only registers.
24 /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
50 RF_CHANNEL( 9) = 0x57,
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/zydas/zd1211rw/
Dzd_rf_uw2453.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
20 /* The 3-wire serial interface provides access to 8 write-only registers.
24 /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
50 RF_CHANNEL( 9) = 0x57,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dste-dma40.txt4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
19 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
19 The first cell is the unique device channel number as indicated by this
31 9: Synchronous Serial Port SSP1
32 10: Multi-Channel Display Engine MCDE RX
[all …]

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