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/kernel/linux/linux-6.6/Documentation/arch/arm64/
Dasymmetric-32bit.rst2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
10 Date: 2021-05-17
15 Some Armv9 SoCs suffer from a big.LITTLE misfeature where only a subset
16 of the CPUs are capable of executing 32-bit user applications. On such
17 a system, Linux by default treats the asymmetry as a "mismatch" and
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
[all …]
/kernel/linux/linux-5.10/include/linux/
Dwait_bit.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Linux wait-bit related types and methods:
21 #define __WAIT_BIT_KEY_INITIALIZER(word, bit) \ argument
22 { .flags = word, .bit_nr = bit, }
26 void __wake_up_bit(struct wait_queue_head *wq_head, void *word, int bit);
29 void wake_up_bit(void *word, int bit);
33 struct wait_queue_head *bit_waitqueue(void *word, int bit);
38 #define DEFINE_WAIT_BIT(name, word, bit) \ argument
40 .key = __WAIT_BIT_KEY_INITIALIZER(word, bit), \
55 * wait_on_bit - wait for a bit to be cleared
[all …]
Dexportfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 * 32bit inode number, 32 bit generation number.
38 * 32bit inode number, 32 bit generation number,
39 * 32 bit parent directory inode number.
44 * 64 bit object ID, 64 bit root object ID,
45 * 32 bit generation number.
50 * 64 bit object ID, 64 bit root object ID,
51 * 32 bit generation number,
52 * 64 bit parent object ID, 32 bit parent generation.
57 * 64 bit object ID, 64 bit root object ID,
[all …]
Dmath64.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
16 * @dividend: unsigned 64bit dividend
17 * @divisor: unsigned 32bit divisor
18 * @remainder: pointer to unsigned 32bit remainder
22 * This is commonly provided by 32bit archs to provide an optimized 64bit
32 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
33 * @dividend: signed 64bit dividend
34 * @divisor: signed 32bit divisor
35 * @remainder: pointer to signed 32bit remainder
[all …]
/kernel/linux/linux-6.6/include/linux/
Dwait_bit.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Linux wait-bit related types and methods:
21 #define __WAIT_BIT_KEY_INITIALIZER(word, bit) \ argument
22 { .flags = word, .bit_nr = bit, }
26 void __wake_up_bit(struct wait_queue_head *wq_head, void *word, int bit);
29 void wake_up_bit(void *word, int bit);
33 struct wait_queue_head *bit_waitqueue(void *word, int bit);
38 #define DEFINE_WAIT_BIT(name, word, bit) \ argument
40 .key = __WAIT_BIT_KEY_INITIALIZER(word, bit), \
55 * wait_on_bit - wait for a bit to be cleared
[all …]
Dmath64.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
36 * @remainder: pointer to signed 32bit remainder
[all …]
Dexportfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 * 32bit inode number, 32 bit generation number.
38 * 32bit inode number, 32 bit generation number,
39 * 32 bit parent directory inode number.
44 * 64 bit object ID, 64 bit root object ID,
45 * 32 bit generation number.
50 * 64 bit object ID, 64 bit root object ID,
51 * 32 bit generation number,
52 * 64 bit parent object ID, 32 bit parent generation.
57 * 64 bit object ID, 64 bit root object ID,
[all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/cec/
Dcec-pin-error-inj.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
6 The CEC Pin Framework is a core CEC framework for CEC hardware that only
7 has low-level support for the CEC bus. Most hardware today will have
8 high-level CEC support where the hardware deals with driving the CEC bus,
10 allows you to connect the CEC pin to a GPIO on e.g. a Raspberry Pi and
11 you have now made a CEC adapter.
17 Currently only the cec-gpio driver (when the CEC line is directly
18 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
23 now an ``error-inj`` file.
27 The error injection commands are not a stable ABI and may change in the
[all …]
/kernel/linux/linux-6.6/Documentation/userspace-api/media/cec/
Dcec-pin-error-inj.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 The CEC Pin Framework is a core CEC framework for CEC hardware that only
9 has low-level support for the CEC bus. Most hardware today will have
10 high-level CEC support where the hardware deals with driving the CEC bus,
12 allows you to connect the CEC pin to a GPIO on e.g. a Raspberry Pi and
13 you have now made a CEC adapter.
19 Currently only the cec-gpio driver (when the CEC line is directly
20 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
25 now an ``error-inj`` file.
29 The error injection commands are not a stable ABI and may change in the
[all …]
/kernel/linux/linux-6.6/drivers/gpio/
Dgpio-104-idi-48.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-IDI-48 family
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
29 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
49 *mask = BIT(line); in idi_48_reg_mask_xlate()
91 .mask = BIT((_id) / 8), \
96 IDI48_REGMAP_IRQ(0), IDI48_REGMAP_IRQ(1), IDI48_REGMAP_IRQ(2), /* 0-2 */
97 IDI48_REGMAP_IRQ(3), IDI48_REGMAP_IRQ(4), IDI48_REGMAP_IRQ(5), /* 3-5 */
[all …]
/kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/
Dcore_feature_dsp.h4 * SPDX-License-Identifier: Apache-2.0
8 * You may obtain a copy of the License at
10 * www.apache.org/licenses/LICENSE-2.0
41 * \brief Functions that generate RISC-V DSP SIMD instructions.
44 …* The following functions generate specified RISC-V SIMD instructions that cannot be directly acce…
47 * - r.H == rH1: r[31:16], r.L == r.H0: r[15:0]
48 * - r.B3: r[31:24], r.B2: r[23:16], r.B1: r[15:8], r.B0: r[7:0]
49 * - r.B[x]: r[(x*8+7):(x*8+0)]
50 * - r.H[x]: r[(x*16+7):(x*16+0)]
51 * - r.W[x]: r[(x*32+31):(x*32+0)]
[all …]
/kernel/linux/linux-5.10/drivers/gpio/
Dgpio-104-idi-48.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-IDI-48 family
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
30 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
37 * struct idi_48_gpio - GPIO device private data structure
43 * @cos_enb: Change-Of-State IRQ enable boundaries mask
75 mask = BIT(offset - i); in idi_48_gpio_get()
77 return !!(inb(idi48gpio->base + base_offset) & mask); in idi_48_gpio_get()
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath11k/
Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
89 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0)
90 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1)
91 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2)
92 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3)
93 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4)
94 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5)
95 #define RX_ATTENTION_INFO1_NON_QOS BIT(6)
96 #define RX_ATTENTION_INFO1_NULL_DATA BIT(7)
[all …]
/kernel/linux/linux-5.10/arch/mips/lib/
Dbitops.c6 * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
16 * __mips_set_bit - Atomically set a bit in memory. This is called by
17 * set_bit() if it cannot find a faster solution.
18 * @nr: the bit to set
23 volatile unsigned long *a = &addr[BIT_WORD(nr)]; in __mips_set_bit() local
24 unsigned int bit = nr % BITS_PER_LONG; in __mips_set_bit() local
28 mask = 1UL << bit; in __mips_set_bit()
30 *a |= mask; in __mips_set_bit()
37 * __mips_clear_bit - Clears a bit in memory. This is called by clear_bit() if
38 * it cannot find a faster solution.
[all …]
/kernel/linux/linux-6.6/arch/mips/lib/
Dbitops.c6 * Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
16 * __mips_set_bit - Atomically set a bit in memory. This is called by
17 * set_bit() if it cannot find a faster solution.
18 * @nr: the bit to set
23 volatile unsigned long *a = &addr[BIT_WORD(nr)]; in __mips_set_bit() local
24 unsigned int bit = nr % BITS_PER_LONG; in __mips_set_bit() local
28 mask = 1UL << bit; in __mips_set_bit()
30 *a |= mask; in __mips_set_bit()
37 * __mips_clear_bit - Clears a bit in memory. This is called by clear_bit() if
38 * it cannot find a faster solution.
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath11k/
Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
88 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0)
89 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1)
90 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2)
91 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3)
92 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4)
93 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5)
94 #define RX_ATTENTION_INFO1_NON_QOS BIT(6)
95 #define RX_ATTENTION_INFO1_NULL_DATA BIT(7)
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath12k/
Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
27 #define RX_MPDU_START_INFO0_FLOW_ID_TOEPLITZ BIT(7)
28 #define RX_MPDU_START_INFO0_PKT_SEL_FP_UCAST_DATA BIT(8)
29 #define RX_MPDU_START_INFO0_PKT_SEL_FP_MCAST_DATA BIT(9)
30 #define RX_MPDU_START_INFO0_PKT_SEL_FP_CTRL_BAR BIT(10)
33 #define RX_MPDU_START_INFO0_MCAST_ECHO_DROP_EN BIT(17)
34 #define RX_MPDU_START_INFO0_WDS_LEARN_DETECT_EN BIT(18)
35 #define RX_MPDU_START_INFO0_INTRA_BSS_CHECK_EN BIT(19)
[all …]
/kernel/linux/linux-5.10/drivers/net/fddi/skfp/h/
Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
31 * Note: The temperature and voltage sensors are relocated on a different
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
[all …]
/kernel/linux/linux-6.6/drivers/net/fddi/skfp/h/
Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
31 * Note: The temperature and voltage sensors are relocated on a different
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
[all …]
/kernel/linux/linux-6.6/arch/ia64/include/asm/
Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 1998-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
23 * set_bit - Atomically set a bit in memory
24 * @nr: the bit to set
30 * restricted to acting on a single-word quantity.
34 * operate on hw-defined data-structures, so we can't easily change these
35 * operations to force a bigger alignment.
37 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
42 __u32 bit, old, new; in set_bit() local
[all …]
/kernel/linux/linux-5.10/arch/ia64/include/asm/
Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 1998-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
23 * set_bit - Atomically set a bit in memory
24 * @nr: the bit to set
30 * restricted to acting on a single-word quantity.
34 * operate on hw-defined data-structures, so we can't easily change these
35 * operations to force a bigger alignment.
37 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
42 __u32 bit, old, new; in set_bit() local
[all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/rc/
Drc-protos.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
9 IR is encoded as a series of pulses and spaces, using a protocol. These
10 protocols can encode e.g. an address (which device should respond) and a
12 across different devices for a given protocol.
14 Therefore out the output of the IR decoder is a scancode; a single u32
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
[all …]
/kernel/linux/linux-6.6/Documentation/userspace-api/media/rc/
Drc-protos.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
9 IR is encoded as a series of pulses and spaces, using a protocol. These
10 protocols can encode e.g. an address (which device should respond) and a
12 across different devices for a given protocol.
14 Therefore out the output of the IR decoder is a scancode; a single u32
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
[all …]
/kernel/linux/linux-5.10/Documentation/staging/
Dcrc32.rst5 A CRC is a long-division remainder. You add the CRC to the message,
6 and the whole thing (message+CRC) is a multiple of the given
10 is used by a lot of hardware implementations, and is why so many
11 protocols put the end-of-frame flag after the CRC.
15 - We're working in binary, so the digits are only 0 and 1, and
16 - When dividing polynomials, there are no carries. Rather than add and
17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
[all …]
/kernel/linux/linux-6.6/Documentation/staging/
Dcrc32.rst5 A CRC is a long-division remainder. You add the CRC to the message,
6 and the whole thing (message+CRC) is a multiple of the given
10 is used by a lot of hardware implementations, and is why so many
11 protocols put the end-of-frame flag after the CRC.
15 - We're working in binary, so the digits are only 0 and 1, and
16 - When dividing polynomials, there are no carries. Rather than add and
17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
[all …]

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