Searched +full:armv8 +full:- +full:based (Results 1 – 25 of 107) sorted by relevance
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| /kernel/linux/linux-6.6/arch/arm64/ |
| D | Kconfig.platforms | 1 # SPDX-License-Identifier: GPL-2.0-only
12 bool "Allwinner sunxi 64-bit SoC Family"
20 This enables support for Allwinner sunxi based SoCs like the A64.
33 This enables support for Apple's in-house ARM SoC family, starting
61 This enables support for Broadcom iProc based SoCs
67 Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
70 This enables support for Broadcom BCA ARM-based broadband chipsets,
74 bool "Broadcom Set-Top-Box SoCs"
79 This enables support for Broadcom's ARMv8 Set Top Box SoCs
108 This enables support for ARMv8 based Samsung Exynos SoC family.
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
260 ARM 64-bit (AArch64) Linux support.
269 depends on $(cc-option,-fpatchable-function-entry=2)
301 # VA_BITS - PAGE_SHIFT - 3
377 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
432 at stage-2.
440 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
445 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
448 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
454 data cache clean-and-invalidate.
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| /kernel/linux/linux-5.10/arch/arm64/ |
| D | Kconfig.platforms | 1 # SPDX-License-Identifier: GPL-2.0-only
17 bool "Allwinner sunxi 64-bit SoC Family"
23 This enables support for Allwinner sunxi based SoCs like the A64.
52 This enables support for Broadcom iProc based SoCs
69 bool "Broadcom Set-Top-Box SoCs"
76 This enables support for Broadcom's ARMv8 Set Top Box SoCs
79 bool "ARMv8 based Samsung Exynos SoC family"
90 This enables support for ARMv8 based Samsung Exynos SoC family.
93 bool "ARMv8 based Microchip Sparx5 SoC family"
97 This enables support for the Microchip Sparx5 ARMv8-based
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
165 if $(cc-option,-fpatchable-function-entry=2)
212 ARM 64-bit (AArch64) Linux support.
244 # VA_BITS - PAGE_SHIFT - 3
337 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
364 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
369 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
372 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
378 data cache clean-and-invalidate.
386 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
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| /kernel/linux/linux-5.10/arch/arm/crypto/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
13 tristate "SHA1 digest algorithm (ARM-asm)"
17 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
27 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
37 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
38 using special ARMv8 Crypto Extensions.
41 tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)"
46 SHA-256 secure hash standard (DFIPS 180-2) implemented
47 using special ARMv8 Crypto Extensions.
50 tristate "SHA-224/256 digest algorithm (ARM-asm and NEON)"
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| /kernel/linux/linux-6.6/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
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| /kernel/linux/linux-5.10/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
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| /kernel/linux/linux-6.6/drivers/perf/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
61 bool "RISC-V PMU framework"
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| /kernel/linux/linux-6.6/Documentation/virt/hyperv/ |
| D | clocks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
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| /kernel/linux/linux-5.10/drivers/perf/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
70 based on the Stream ID of the corresponding master.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/nuvoton/ |
| D | nuvoton,ma35d1.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton MA35 series SoC based platforms
10 - Jacky Huang <ychuang3@nuvoton.com>
13 Boards with an ARMv8 based Nuvoton MA35 series SoC shall have
22 - description: MA35D1 based boards
24 - enum:
25 - nuvoton,ma35d1-iot
26 - nuvoton,ma35d1-som
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| /kernel/linux/linux-5.10/drivers/soc/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
15 # There is no need to enable these drivers for ARMv8
17 bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST
31 # There is no need to enable these drivers for ARMv8
33 bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST
48 Resume code. See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
58 Note, this currently only works for S3C64XX based SMDK boards.
73 See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
85 See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
27 Build the s3c2410 clock driver based on the common clock framework.
34 Temporary symbol to build the dclk driver based on the common clock
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| /kernel/linux/linux-6.6/arch/arm64/crypto/ |
| D | polyval-ce-glue.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Glue code for POLYVAL using ARMv8 Crypto Extensions
5 * Copyright (c) 2007 Nokia Siemens Networks - Mikko Herranen <mh1@iki.fi>
12 * Glue code based on ghash-clmulni-intel_glue.c.
15 * ARMv8 Crypto Extensions instructions to implement the finite field operations.
56 polyval_update_non4k(keys->key_powers[NUM_KEY_POWERS-1], in, in internal_polyval_update()
79 return -EINVAL; in polyval_arm64_setkey()
81 memcpy(tctx->key_powers[NUM_KEY_POWERS-1], key, POLYVAL_BLOCK_SIZE); in polyval_arm64_setkey()
83 for (i = NUM_KEY_POWERS-2; i >= 0; i--) { in polyval_arm64_setkey()
84 memcpy(tctx->key_powers[i], key, POLYVAL_BLOCK_SIZE); in polyval_arm64_setkey()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | microchip,sparx5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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| D | coresight-cpu-debug.txt | 3 CoreSight CPU debug component are compliant with the ARMv8 architecture
5 external debug module is mainly used for two modes: self-hosted debug and
8 debug module provides sample-based profiling extension, which can be used
14 - compatible : should be "arm,coresight-cpu-debug"; supplemented with
18 - reg : physical base address and length of the register set.
20 - clocks : the clock associated to this component.
22 - clock-names : the name of the clock referenced by the code. Since we are
29 - cpu : the CPU phandle the debug module is affined to. Do not assume it
34 - power-domains: a phandle to the debug power domain. We use "power-domains"
44 compatible = "arm,coresight-cpu-debug","arm,primecell";
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/ |
| D | microchip,sparx5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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| D | arm,coresight-cpu-debug.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight CPU debug component are compliant with the ARMv8 architecture
18 external debug module is mainly used for two modes: self-hosted debug and
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| /kernel/linux/linux-5.10/drivers/soc/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
21 Support for NVIDIA Tegra AP20 and T20 processors, based on the
35 Support for NVIDIA Tegra T30 processor family, based on the
47 Support for NVIDIA Tegra T114 processor family, based on the
58 Support for NVIDIA Tegra T124 processor family, based on the
63 # 64-bit ARM SoCs
72 Enable support for NVIDIA Tegra132 SoC, based on the Denver
73 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
75 Tegra124's "4+1" Cortex-A15 CPU complex.
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| /kernel/linux/linux-6.6/drivers/soc/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
21 Support for NVIDIA Tegra AP20 and T20 processors, based on the
35 Support for NVIDIA Tegra T30 processor family, based on the
47 Support for NVIDIA Tegra T114 processor family, based on the
58 Support for NVIDIA Tegra T124 processor family, based on the
63 # 64-bit ARM SoCs
72 Enable support for NVIDIA Tegra132 SoC, based on the Denver
73 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
75 Tegra124's "4+1" Cortex-A15 CPU complex.
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| /kernel/linux/linux-5.10/Documentation/arm64/ |
| D | pointer-authentication.rst | 7 Date: 2017-07-19
14 ---------------------
16 The ARMv8.3 Pointer Authentication extension adds primitives that can be
27 of high-order bits of the pointer, which varies dependent on the
36 The extension provides five separate keys to generate PACs - two for
42 -------------
56 Recent versions of GCC can compile code with APIAKey-based return
57 address protection when passed the -msign-return-address option. This
58 uses instructions in the HINT space (unless -march=armv8.3-a or higher
70 ---------
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| D | arm-acpi.rst | 2 ACPI on ARMv8 Servers
5 ACPI can be used for ARMv8 general purpose servers designed to follow
11 The ARMv8 kernel implements the reduced hardware model of ACPI version
17 If an ARMv8 system does not meet the requirements of the SBSA and SBBR,
22 industry-standard ARMv8 servers, they also apply to more than one operating
24 ACPI and Linux only, on an ARMv8 system -- that is, what Linux expects of
29 ----------------
32 exist in Linux for describing non-enumerable hardware, after all. In this
34 reasoning behind ACPI on ARMv8 servers. Actually, we snitch a good portion
39 - ACPI’s byte code (AML) allows the platform to encode hardware behavior,
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| D | memory-tagging-extension.rst | 8 Date: 2020-02-25
16 ARMv8.5 based processors introduce the Memory Tagging Extension (MTE)
17 feature. MTE is built on top of the ARMv8.0 virtual address tagging TBI
18 (Top Byte Ignore) feature and allows software to access a 4-bit
19 allocation tag for each 16-byte granule in the physical address space.
20 Such memory range must be mapped with the Normal-Tagged memory
21 attribute. A logical tag is derived from bits 59-56 of the virtual
34 --------
40 ``PROT_MTE`` - Pages allow access to the MTE allocation tags.
43 user address space and preserved on copy-on-write. ``MAP_SHARED`` is
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| /kernel/linux/linux-6.6/Documentation/arch/arm64/ |
| D | memory-tagging-extension.rst | 8 Date: 2020-02-25
16 ARMv8.5 based processors introduce the Memory Tagging Extension (MTE)
17 feature. MTE is built on top of the ARMv8.0 virtual address tagging TBI
18 (Top Byte Ignore) feature and allows software to access a 4-bit
19 allocation tag for each 16-byte granule in the physical address space.
20 Such memory range must be mapped with the Normal-Tagged memory
21 attribute. A logical tag is derived from bits 59-56 of the virtual
34 --------
40 ``PROT_MTE`` - Pages allow access to the MTE allocation tags.
43 user address space and preserved on copy-on-write. ``MAP_SHARED`` is
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| /kernel/linux/linux-6.6/lib/ |
| D | Kconfig.kasan | 1 # SPDX-License-Identifier: GPL-2.0-only
23 def_bool $(cc-option, -fsanitize=kernel-address)
26 def_bool $(cc-option, -fsanitize=kernel-hwaddress)
43 Enables KASAN (Kernel Address Sanitizer) - a dynamic memory safety
44 error detector designed to find out-of-bounds and use-after-free bugs.
46 See Documentation/dev-tools/kasan.rst for details.
53 …def_bool (CC_IS_CLANG && $(cc-option,-fsanitize=kernel-address -mllvm -asan-kernel-mem-intrinsic-p…
54 (CC_IS_GCC && $(cc-option,-fsanitize=kernel-address --param asan-kernel-mem-intrinsic-prefix=1))
69 2. Software Tag-Based KASAN (arm64 only, based on software memory
72 3. Hardware Tag-Based KASAN (arm64 only, based on hardware memory
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