| /kernel/linux/linux-6.6/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 20 struct iproc_asiu *asiu; member
39 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable() local
42 /* some clocks at the ASIU level are always enabled */ in iproc_asiu_clk_enable()
46 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
48 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
56 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_disable() local
59 /* some clocks at the ASIU level are always enabled */ in iproc_asiu_clk_disable()
63 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_disable()
65 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_disable()
72 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_recalc_rate() local
[all …]
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| D | clk-iproc.h | 22 /* PLL that requires gating through ASIU */
98 * Clock gating control at the top ASIU level
158 struct iproc_asiu_gate asiu; member
191 * Divisor of the ASIU clocks
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| D | clk-iproc-pll.c | 181 val = readl(pll->asiu_base + ctrl->asiu.offset); in __pll_disable()
182 val &= ~(1 << ctrl->asiu.en_shift); in __pll_disable()
183 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); in __pll_disable()
223 /* certain PLLs also need to be ungated from the ASIU top level */ in __pll_enable()
225 val = readl(pll->asiu_base + ctrl->asiu.offset); in __pll_enable()
226 val |= (1 << ctrl->asiu.en_shift); in __pll_enable()
227 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); in __pll_enable()
754 /* some PLLs require gating control at the top ASIU level */ in iproc_pll_clk_setup()
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| D | Makefile | 9 obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
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| D | clk-cygnus.c | 187 .asiu = ASIU_GATE_VAL(0x0, 3),
260 CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
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| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 30 struct iproc_asiu *asiu; member
49 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable() local
52 /* some clocks at the ASIU level are always enabled */ in iproc_asiu_clk_enable()
56 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
58 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
66 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_disable() local
69 /* some clocks at the ASIU level are always enabled */ in iproc_asiu_clk_disable()
73 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_disable()
75 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_disable()
82 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_recalc_rate() local
[all …]
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| D | clk-iproc.h | 32 /* PLL that requires gating through ASIU */
108 * Clock gating control at the top ASIU level
168 struct iproc_asiu_gate asiu; member
201 * Divisor of the ASIU clocks
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| D | clk-iproc-pll.c | 191 val = readl(pll->asiu_base + ctrl->asiu.offset); in __pll_disable()
192 val &= ~(1 << ctrl->asiu.en_shift); in __pll_disable()
193 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); in __pll_disable()
233 /* certain PLLs also need to be ungated from the ASIU top level */ in __pll_enable()
235 val = readl(pll->asiu_base + ctrl->asiu.offset); in __pll_enable()
236 val |= (1 << ctrl->asiu.en_shift); in __pll_enable()
237 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); in __pll_enable()
764 /* some PLLs require gating control at the top ASIU level */ in iproc_pll_clk_setup()
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| D | Makefile | 8 obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
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| D | clk-cygnus.c | 197 .asiu = ASIU_GATE_VAL(0x0, 3),
270 CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | brcm,iproc-clocks.txt | 48 Required properties for ASIU clocks:
50 ASIU clocks are a special case. These clocks are derived directly from the
54 Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU
55 clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
58 Have a value of <1> since there are more than 1 ASIU clocks
62 clock control registers required for ASIU clocks
65 The input parent clock phandle for the ASIU clock, i.e., the onboard
69 An ordered list of strings defining the names of the ASIU clocks
81 compatible = "brcm,cygnus-asiu-clk";
94 "brcm,cygnus-asiu-clk"
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | brcm,iproc-clocks.yaml | 19 ASIU clocks are a special case. These clocks are derived directly from the
30 - brcm,cygnus-asiu-clk
56 - description: ASIU or split status register
59 description: The input parent clock phandle for the PLL / ASIU clock. For
97 - brcm,cygnus-asiu-clk
113 keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
114 adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
115 pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
406 compatible = "brcm,cygnus-asiu-clk";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,iproc-gpio.txt | 13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
97 compatible = "brcm,cygnus-asiu-gpio";
118 /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,iproc-gpio.txt | 13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
97 compatible = "brcm,cygnus-asiu-gpio";
118 /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */
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| /kernel/linux/linux-5.10/drivers/pinctrl/bcm/ |
| D | Kconfig | 45 The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU
46 GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and
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| D | pinctrl-iproc-gpio.c | 8 * GPIO controllers on Iproc including the ASIU GPIO controller, the
46 /* drive strength control for ASIU GPIO */
774 { .compatible = "brcm,cygnus-asiu-gpio" },
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| D | pinctrl-cygnus-mux.c | 20 * function, and therefore be controlled by the Cygnus ASIU GPIO controller
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| /kernel/linux/linux-6.6/drivers/pinctrl/bcm/ |
| D | Kconfig | 122 The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU
123 GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and
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| D | pinctrl-iproc-gpio.c | 8 * GPIO controllers on Iproc including the ASIU GPIO controller, the
49 /* drive strength control for ASIU GPIO */
797 { .compatible = "brcm,cygnus-asiu-gpio" },
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| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| D | bcm-cygnus.h | 63 /* ASIU clock ID */
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | bcm-cygnus.h | 63 /* ASIU clock ID */
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm-cygnus-clock.dtsi | 118 compatible = "brcm,cygnus-asiu-clk";
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| D | bcm-cygnus.dtsi | 514 compatible = "brcm,cygnus-asiu-gpio";
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/ |
| D | bcm-cygnus-clock.dtsi | 118 compatible = "brcm,cygnus-asiu-clk";
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| D | bcm-cygnus.dtsi | 516 compatible = "brcm,cygnus-asiu-gpio";
|