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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/
Drenesas,bsc.yaml3 $id: http://devicetree.org/schemas/bus/renesas,bsc.yaml#
6 title: Renesas Bus State Controller (BSC)
12 The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
18 While the BSC is a fairly simple memory-mapped bus, it may be part of a
20 connected to the BSC can be accessed, the PM domain containing the BSC
21 must be powered on, and the functional clock driving the BSC must be
24 The bindings for the BSC extend the bindings for "simple-pm-bus".
33 - renesas,bsc-r8a73a4 # R-Mobile APE6 (r8a73a4)
34 - renesas,bsc-sh73a0 # SH-Mobile AG5 (sh73a0)
35 - const: renesas,bsc
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/
Drenesas,bsc.yaml3 $id: http://devicetree.org/schemas/bus/renesas,bsc.yaml#
6 title: Renesas Bus State Controller (BSC)
12 The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
18 While the BSC is a fairly simple memory-mapped bus, it may be part of a
20 connected to the BSC can be accessed, the PM domain containing the BSC
21 must be powered on, and the functional clock driving the BSC must be
24 The bindings for the BSC extend the bindings for "simple-pm-bus".
33 - renesas,bsc-r8a73a4 # R-Mobile APE6 (r8a73a4)
34 - renesas,bsc-sh73a0 # SH-Mobile AG5 (sh73a0)
35 - const: renesas,bsc
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Drenesas,h8300-bsc.txt4 - compatible: Must be "renesas,h8300-bsc".
5 - reg: Base address and length of BSC registers.
8 bsc: memory-controller@fee01e {
9 compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
/kernel/linux/linux-5.10/drivers/staging/board/
Dboard.c122 int __init board_staging_register_clock(const struct board_staging_clk *bsc) in board_staging_register_clock() argument
126 pr_debug("Aliasing clock %s for con_id %s dev_id %s\n", bsc->clk, in board_staging_register_clock()
127 bsc->con_id, bsc->dev_id); in board_staging_register_clock()
128 error = clk_add_alias(bsc->con_id, bsc->dev_id, bsc->clk, NULL); in board_staging_register_clock()
130 pr_err("Failed to alias clock %s (%d)\n", bsc->clk, error); in board_staging_register_clock()
Dboard.h30 int board_staging_register_clock(const struct board_staging_clk *bsc);
/kernel/linux/linux-6.6/drivers/staging/board/
Dboard.c122 int __init board_staging_register_clock(const struct board_staging_clk *bsc) in board_staging_register_clock() argument
126 pr_debug("Aliasing clock %s for con_id %s dev_id %s\n", bsc->clk, in board_staging_register_clock()
127 bsc->con_id, bsc->dev_id); in board_staging_register_clock()
128 error = clk_add_alias(bsc->con_id, bsc->dev_id, bsc->clk, NULL); in board_staging_register_clock()
130 pr_err("Failed to alias clock %s (%d)\n", bsc->clk, error); in board_staging_register_clock()
Dboard.h30 int board_staging_register_clock(const struct board_staging_clk *bsc);
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Dbrcm,brcmstb-i2c.yaml7 title: Broadcom STB BSC IIC Master Controller
26 - description: BSC register range
31 - const: bsc
93 reg-names = "bsc", "auto-i2c";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/i2c/
Dbrcm,brcmstb-i2c.yaml7 title: Broadcom STB BSC IIC Master Controller
25 - description: BSC register range
30 - const: bsc
92 reg-names = "bsc", "auto-i2c";
/kernel/linux/linux-5.10/arch/h8300/boot/dts/
Dh8300h_sim.dts60 bsc: memory-controller@fee01e { label
61 compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
Dh8s_sim.dts66 bsc: memory-controller@fffec0 { label
67 compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
Dedosk2674.dts67 bsc: memory-controller@fffec0 { label
68 compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
/kernel/linux/linux-5.10/drivers/i2c/busses/
Di2c-brcmstb.c30 * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
39 /* BSC CTL register field definitions */
69 /* BSC data transfer direction */
72 /* BSC data transfer direction combined format */
79 /* BSC block register map structure to cache fields to be written */
206 /* Enable BSC CTL interrupt line */ in brcmstb_i2c_enable_disable_irq()
209 /* Disable BSC CTL interrupt line */ in brcmstb_i2c_enable_disable_irq()
304 /* enable BSC CTL interrupt line */ in brcmstb_send_i2c_cmd()
333 /* Actual data transfer through the BSC master */
652 /* disable the bsc interrupt line */ in brcmstb_i2c_probe()
/kernel/linux/linux-6.6/drivers/i2c/busses/
Di2c-brcmstb.c19 * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
28 /* BSC CTL register field definitions */
58 /* BSC data transfer direction */
61 /* BSC data transfer direction combined format */
68 /* BSC block register map structure to cache fields to be written */
195 /* Enable BSC CTL interrupt line */ in brcmstb_i2c_enable_disable_irq()
198 /* Disable BSC CTL interrupt line */ in brcmstb_i2c_enable_disable_irq()
293 /* enable BSC CTL interrupt line */ in brcmstb_send_i2c_cmd()
322 /* Actual data transfer through the BSC master */
635 /* disable the bsc interrupt line */ in brcmstb_i2c_probe()
/kernel/linux/linux-5.10/arch/h8300/kernel/
Dsetup.c184 struct device_node *bsc; in access_timing() local
190 bsc = of_find_compatible_node(NULL, NULL, "renesas,h8300-bsc"); in access_timing()
191 base = of_iomap(bsc, 0); in access_timing()
/kernel/linux/linux-5.10/arch/sh/include/cpu-sh4/cpu/
Dsh7722.h10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
148 /* BSC */
Dsh7723.h10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
247 /* BSC */
Dsh7724.h10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
113 /* BSC (PTA/PTB/PTJ/PTQ/PTR/PTT) */
/kernel/linux/linux-6.6/arch/sh/include/cpu-sh4/cpu/
Dsh7722.h10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
148 /* BSC */
Dsh7723.h10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
247 /* BSC */
Dsh7724.h10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
113 /* BSC (PTA/PTB/PTJ/PTQ/PTR/PTT) */
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh2a/
Dsetup-sh7206.c30 CMT0, CMT1, BSC, WDT, enumerator
61 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
112 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
Dsetup-sh7203.c22 USB, LCDC, CMT0, CMT1, BSC, WDT, enumerator
63 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
144 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2a/
Dsetup-sh7206.c30 CMT0, CMT1, BSC, WDT, enumerator
61 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
112 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
Dsetup-sh7203.c22 USB, LCDC, CMT0, CMT1, BSC, WDT, enumerator
63 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
144 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },

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