| /kernel/linux/linux-6.6/arch/arm/mm/ |
| D | cache-fa.S | 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
98 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
134 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
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| D | proc-arm946.S | 57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
328 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-xsc3.S | 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
202 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
204 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
231 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
252 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
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| D | cache-v6.S | 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
145 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
150 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
|
| D | proc-arm940.S | 50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
281 mcr p15, 0, r0, c6, c5, 0
287 mcr p15, 0, r0, c6, c5, 1
319 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
320 mcr p15, 0, r0, c5, c0, 1
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| D | proc-fa526.S | 108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
111 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
150 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
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| D | cache-v4wt.S | 48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
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| D | proc-arm926.S | 109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
364 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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| D | proc-arm925.S | 143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
207 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
242 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
266 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
403 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
| /kernel/linux/linux-5.10/arch/arm/mm/ |
| D | cache-fa.S | 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
71 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
97 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
99 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
128 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
133 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
135 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
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| D | proc-arm946.S | 57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
328 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| D | proc-xsc3.S | 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
202 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
204 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
231 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
252 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
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| D | cache-v6.S | 40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
143 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
|
| D | proc-arm940.S | 50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
281 mcr p15, 0, r0, c6, c5, 0
287 mcr p15, 0, r0, c6, c5, 1
319 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
320 mcr p15, 0, r0, c5, c0, 1
|
| D | proc-fa526.S | 108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
111 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
150 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
|
| D | cache-v4wt.S | 48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
|
| D | proc-arm926.S | 109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
364 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
| D | proc-arm925.S | 143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
207 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
242 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
266 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
403 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
| /kernel/linux/linux-6.6/arch/s390/crypto/ |
| D | chacha-s390.S | 467 #define C5 %v22 macro
519 VLR C5,K2
550 VAF C5,C5,D5
556 VX B5,B5,C5
588 VAF C5,C5,D5
594 VX B5,B5,C5
607 VSLDB C5,C5,C5,8
645 VAF C5,C5,D5
651 VX B5,B5,C5
683 VAF C5,C5,D5
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | nvidia,tegra194-pcie.txt | 17 TEGRA194_POWER_DOMAIN_PCIEX8A: C5
54 5: C5
91 In Tegra194, Only controllers C0, C4 & C5 support EP mode.
101 It is mandatory for C5 controller and optional for other controllers.
104 It is mandatory for C5 controller and optional for other controllers.
111 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
112 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
124 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
127 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
134 NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
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| /kernel/linux/linux-6.6/arch/arm/include/asm/hardware/ |
| D | cp14.h | 47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
62 #define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
78 #define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
94 #define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
110 #define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
127 #define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
142 #define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
167 #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
183 #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
[all …]
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| /kernel/linux/linux-5.10/arch/arm/include/asm/hardware/ |
| D | cp14.h | 47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
62 #define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
78 #define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
94 #define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
110 #define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
127 #define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
142 #define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
167 #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
183 #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
[all …]
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| /kernel/liteos_a/arch/arm/arm/include/ |
| D | arm.h | 146 __asm__ volatile("mrc p15, 0, %0, c5,c0,0" : "=r"(val)); in OsArmReadDfsr()
152 __asm__ volatile("mcr p15, 0, %0, c5,c0,0" ::"r"(val)); in OsArmWriteDfsr()
159 __asm__ volatile("mrc p15, 0, %0, c5,c0,1" : "=r"(val)); in OsArmReadIfsr()
165 __asm__ volatile("mcr p15, 0, %0, c5,c0,1" ::"r"(val)); in OsArmWriteIfsr()
445 __asm__ volatile("mrc p15, 0, %0, c7,c5,6" : "=r"(val)); in OsArmReadBpiall()
451 __asm__ volatile("mcr p15, 0, %0, c7,c5,6" ::"r"(val)); in OsArmWriteBpiall()
458 __asm__ volatile("mrc p15, 0, %0, c7,c5,7" : "=r"(val)); in OsArmReadBpimva()
464 __asm__ volatile("mcr p15, 0, %0, c7,c5,7" ::"r"(val)); in OsArmWriteBpimva()
536 __asm__ volatile("mrc p15, 0, %0, c8,c5,0" : "=r"(val)); in OsArmReadItlbiall()
542 __asm__ volatile("mcr p15, 0, %0, c8,c5,0" ::"r"(val)); in OsArmWriteItlbiall()
[all …]
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| /kernel/linux/linux-6.6/arch/arm/include/asm/ |
| D | tlbflush.h | 323 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero); in __local_flush_tlb_all()
370 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero); in __local_flush_tlb_mm()
376 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid); in __local_flush_tlb_mm()
424 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr); in __local_flush_tlb_page()
426 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); in __local_flush_tlb_page()
431 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr); in __local_flush_tlb_page()
479 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr); in __local_flush_tlb_kernel_page()
481 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); in __local_flush_tlb_kernel_page()
485 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr); in __local_flush_tlb_kernel_page()
534 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); in __local_flush_bp_all()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | tlbflush.h | 330 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero); in __local_flush_tlb_all()
377 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero); in __local_flush_tlb_mm()
383 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid); in __local_flush_tlb_mm()
431 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr); in __local_flush_tlb_page()
433 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); in __local_flush_tlb_page()
438 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr); in __local_flush_tlb_page()
486 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr); in __local_flush_tlb_kernel_page()
488 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); in __local_flush_tlb_kernel_page()
492 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr); in __local_flush_tlb_kernel_page()
541 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); in __local_flush_bp_all()
[all …]
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