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Searched full:c7 (Results 1 – 25 of 468) sorted by relevance

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/kernel/linux/linux-6.6/arch/arm/mm/
D	proc-arm1020.S	`85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 145 mcr p15, 0, ip, c7, c10, 4 @ drain WB 153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]`
D	proc-arm926.S	69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 134 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	proc-mohawk.S	62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 117 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer 138 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry [all …]
D	proc-arm925.S	109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 110 mcr p15, 0, ip, c7, c10, 4 @ drain WB 112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 170 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	cache-fa.S	44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 65 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 69 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 91 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 97 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier [all …]
D	proc-arm946.S	`57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache 115 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]`
D	proc-arm920.S	77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 78 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-arm922.S	79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 80 mcr p15, 0, ip, c7, c10, 4 @ drain WB 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	cache-v6.S	42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 66 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 136 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 143 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer [all …]
D	proc-fa526.S	58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 87 mcr p15, 0, r0, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 110 mcr p15, 0, ip, c7, c10, 4 @ data write barrier [all …]
D	proc-feroceon.S	73 mcr p15, 0, r0, c7, c10, 4 @ drain WB 95 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 96 mcr p15, 0, ip, c7, c10, 4 @ drain WB 98 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 116 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 127 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 153 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 161 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 162 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	proc-arm1022.S	85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache [all …]
/kernel/linux/linux-5.10/arch/arm/mm/
D	proc-arm1020.S	`85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 145 mcr p15, 0, ip, c7, c10, 4 @ drain WB 153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]`
D	proc-arm926.S	69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 134 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	proc-mohawk.S	62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 117 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer 138 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry [all …]
D	proc-arm925.S	109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 110 mcr p15, 0, ip, c7, c10, 4 @ drain WB 112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 170 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	cache-fa.S	45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 70 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 71 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 92 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 97 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 98 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier [all …]
D	proc-arm946.S	`57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache 115 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]`
D	proc-arm920.S	77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 78 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-arm922.S	79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 80 mcr p15, 0, ip, c7, c10, 4 @ drain WB 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	cache-v6.S	40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 64 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 71 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 134 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 141 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer [all …]
D	proc-fa526.S	58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 87 mcr p15, 0, r0, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 110 mcr p15, 0, ip, c7, c10, 4 @ data write barrier [all …]
D	proc-feroceon.S	69 mcr p15, 0, r0, c7, c10, 4 @ drain WB 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 112 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 113 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 149 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 157 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	proc-arm1022.S	85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm1026.S	85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate 146 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 148 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache [all …]

12 3 4 5 6 7 8 9 10 >>...19