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Searched full:cdr (Results 1 – 25 of 142) sorted by relevance

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/kernel/linux/linux-6.6/drivers/crypto/inside-secure/
Dsafexcel_ring.c14 struct safexcel_desc_ring *cdr, in safexcel_init_ring_descriptors() argument
22 cdr->offset = priv->config.cd_offset; in safexcel_init_ring_descriptors()
23 cdr->base = dmam_alloc_coherent(priv->dev, in safexcel_init_ring_descriptors()
24 cdr->offset * EIP197_DEFAULT_RING_SIZE, in safexcel_init_ring_descriptors()
25 &cdr->base_dma, GFP_KERNEL); in safexcel_init_ring_descriptors()
26 if (!cdr->base) in safexcel_init_ring_descriptors()
28 cdr->write = cdr->base; in safexcel_init_ring_descriptors()
29 cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1); in safexcel_init_ring_descriptors()
30 cdr->read = cdr->base; in safexcel_init_ring_descriptors()
33 cdr->shoffset = priv->config.cdsh_offset; in safexcel_init_ring_descriptors()
[all …]
/kernel/linux/linux-5.10/drivers/crypto/inside-secure/
Dsafexcel_ring.c14 struct safexcel_desc_ring *cdr, in safexcel_init_ring_descriptors() argument
22 cdr->offset = priv->config.cd_offset; in safexcel_init_ring_descriptors()
23 cdr->base = dmam_alloc_coherent(priv->dev, in safexcel_init_ring_descriptors()
24 cdr->offset * EIP197_DEFAULT_RING_SIZE, in safexcel_init_ring_descriptors()
25 &cdr->base_dma, GFP_KERNEL); in safexcel_init_ring_descriptors()
26 if (!cdr->base) in safexcel_init_ring_descriptors()
28 cdr->write = cdr->base; in safexcel_init_ring_descriptors()
29 cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1); in safexcel_init_ring_descriptors()
30 cdr->read = cdr->base; in safexcel_init_ring_descriptors()
33 cdr->shoffset = priv->config.cdsh_offset; in safexcel_init_ring_descriptors()
[all …]
/kernel/linux/linux-5.10/drivers/net/can/sja1000/
Dsja1000_isa.c35 static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; variable
56 module_param_array(cdr, byte, NULL, 0444);
57 MODULE_PARM_DESC(cdr, "Clock divider register "
190 if (cdr[idx] != 0xff) in sja1000_isa_probe()
191 priv->cdr = cdr[idx]; in sja1000_isa_probe()
192 else if (cdr[0] != 0xff) in sja1000_isa_probe()
193 priv->cdr = cdr[0]; in sja1000_isa_probe()
195 priv->cdr = CDR_DEFAULT; in sja1000_isa_probe()
Dsja1000_platform.c116 priv->cdr = pdata->cdr; in sp_populate()
182 priv->cdr |= divider / 2 - 1; in sp_populate_of()
184 priv->cdr |= CDR_CLKOUT_MASK; in sp_populate_of()
186 priv->cdr |= CDR_CLK_OFF; /* default */ in sp_populate_of()
190 priv->cdr |= CDR_CBP; /* default */ in sp_populate_of()
/kernel/linux/linux-6.6/drivers/net/can/sja1000/
Dsja1000_isa.c35 static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; variable
56 module_param_array(cdr, byte, NULL, 0444);
57 MODULE_PARM_DESC(cdr, "Clock divider register "
190 if (cdr[idx] != 0xff) in sja1000_isa_probe()
191 priv->cdr = cdr[idx]; in sja1000_isa_probe()
192 else if (cdr[0] != 0xff) in sja1000_isa_probe()
193 priv->cdr = cdr[0]; in sja1000_isa_probe()
195 priv->cdr = CDR_DEFAULT; in sja1000_isa_probe()
Dsja1000_platform.c118 priv->cdr = pdata->cdr; in sp_populate()
186 priv->cdr |= divider / 2 - 1; in sp_populate_of()
188 priv->cdr |= CDR_CLKOUT_MASK; in sp_populate_of()
190 priv->cdr |= CDR_CLK_OFF; /* default */ in sp_populate_of()
194 priv->cdr |= CDR_CBP; /* default */ in sp_populate_of()
/kernel/linux/linux-6.6/arch/mips/cavium-octeon/executive/
Dcvmx-helper-errata.c43 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
45 * CDR for the specified QLM.
47 * @qlm: QLM to disable 2nd order CDR for.
/kernel/linux/linux-5.10/arch/mips/cavium-octeon/executive/
Dcvmx-helper-errata.c43 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
45 * CDR for the specified QLM.
47 * @qlm: QLM to disable 2nd order CDR for.
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Damd-xgbe.txt46 - amd,serdes-cdr-rate: CDR rate speed selection
71 amd,serdes-cdr-rate = <2>, <2>, <7>;
Dcortina.txt7 devices, equipped with clock and data recovery (CDR) circuits. These
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Damd-xgbe.txt46 - amd,serdes-cdr-rate: CDR rate speed selection
71 amd,serdes-cdr-rate = <2>, <2>, <7>;
Dcortina.txt7 devices, equipped with clock and data recovery (CDR) circuits. These
/kernel/linux/linux-5.10/drivers/ide/
Dtrm290.c63 * bit7 1=autoincrement CPR bits 2-0 after each access of CDR
68 * bits2-0 register index for accesses through CDR port
70 * trm290_base+0 "CDR" Config Data Register (word)
117 * Suggested CDR programming for PIO mode0 (600ns):
121 * Suggested CDR programming for PIO mode3 (180ns):
125 * Suggested CDR programming for PIO mode4 (120ns):
/kernel/linux/linux-5.10/drivers/crypto/mediatek/
Dmtk-platform.c82 * Command Descriptor Ring Manager(CDR Manager) - keeps track of how many
83 * CD the host has prepared in the CDR. It monitors the fill level of its
91 * Result Descriptor Ring Manager(RDR Manager) - same as CDR Manager,
214 /* Clear CDR count */ in mtk_cmd_desc_ring_setup()
222 /* Configure CDR host address space */ in mtk_cmd_desc_ring_setup()
228 /* Clear and disable all CDR interrupts */ in mtk_cmd_desc_ring_setup()
/kernel/linux/linux-6.6/drivers/infiniband/hw/hfi1/
Dplatform.c295 /* RX CDR present, bypass supported */ in apply_rx_cdr()
299 /* Power class <= 3, ignore config & turn RX CDR on */ in apply_rx_cdr()
321 /* Expand cdr setting to all 4 lanes */ in apply_rx_cdr()
329 /* Preserve current TX CDR status */ in apply_rx_cdr()
346 /* TX CDR present, bypass supported */ in apply_tx_cdr()
350 /* Power class <= 3, ignore config & turn TX CDR on */ in apply_tx_cdr()
373 /* Expand cdr setting to all 4 lanes */ in apply_tx_cdr()
380 /* Preserve current/determined RX CDR status */ in apply_tx_cdr()
/kernel/linux/linux-5.10/drivers/infiniband/hw/hfi1/
Dplatform.c337 /* RX CDR present, bypass supported */ in apply_rx_cdr()
341 /* Power class <= 3, ignore config & turn RX CDR on */ in apply_rx_cdr()
363 /* Expand cdr setting to all 4 lanes */ in apply_rx_cdr()
371 /* Preserve current TX CDR status */ in apply_rx_cdr()
388 /* TX CDR present, bypass supported */ in apply_tx_cdr()
392 /* Power class <= 3, ignore config & turn TX CDR on */ in apply_tx_cdr()
415 /* Expand cdr setting to all 4 lanes */ in apply_tx_cdr()
422 /* Preserve current/determined RX CDR status */ in apply_tx_cdr()
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amd/
Damd-seattle-xgbe-b.dtsi49 amd,serdes-cdr-rate = <2>, <2>, <7>;
75 amd,serdes-cdr-rate = <2>, <2>, <7>;
/kernel/linux/linux-6.6/arch/arm64/boot/dts/amd/
Damd-seattle-xgbe-b.dtsi49 amd,serdes-cdr-rate = <2>, <2>, <7>;
75 amd,serdes-cdr-rate = <2>, <2>, <7>;
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
Dparade-ps8622.c110 * [3:2] CDR tune wait cycle before measure for fine tune in ps8622_send_config()
127 /* 2.7G CDR settings: NOF=40LSB for HBR CDR setting */ in ps8622_send_config()
142 /* 1.62G CDR settings: [5:2]NOF=64LSB [1:0]DCO scale is 2/5 */ in ps8622_send_config()
/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
Dparade-ps8622.c111 * [3:2] CDR tune wait cycle before measure for fine tune in ps8622_send_config()
128 /* 2.7G CDR settings: NOF=40LSB for HBR CDR setting */ in ps8622_send_config()
143 /* 1.62G CDR settings: [5:2]NOF=64LSB [1:0]DCO scale is 2/5 */ in ps8622_send_config()
/kernel/linux/linux-6.6/include/linux/can/platform/
Dsja1000.h33 u8 cdr; /* clock divider register */ member
/kernel/linux/linux-5.10/include/linux/can/platform/
Dsja1000.h33 u8 cdr; /* clock divider register */ member
/kernel/linux/linux-5.10/drivers/net/phy/
Dcortina.c97 MODULE_DESCRIPTION("Cortina EDC CDR 10G Ethernet PHY driver");
/kernel/linux/linux-6.6/drivers/net/phy/
Dcortina.c97 MODULE_DESCRIPTION("Cortina EDC CDR 10G Ethernet PHY driver");
/kernel/linux/linux-6.6/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c301 pr_debug("XGBE: CDR centered, DLPF: %4d,%d,%d.\n", in netcp_xgbe_serdes_reset_cdr()
341 /* if no lock, then reset CDR */ in netcp_xgbe_check_link_status()
361 /* Lost the block lock, reset CDR if it is in netcp_xgbe_check_link_status()

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