Searched full:cm2 (Results 1 – 25 of 43) sorted by relevance
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | cm2_44xx.h | 3 * OMAP44xx CM2 instance offset macros
25 /* CM2 base address */
31 /* CM2 instances */
46 /* CM2 clockdomain register offsets (from instance start) */
65 /* CM2 */
67 /* CM2.OCP_SOCKET_CM2 register offsets */
73 /* CM2.CKGEN_CM2 register offsets */
153 /* CM2.ALWAYS_ON_CM2 register offsets */
167 /* CM2.CORE_CM2 register offsets */
251 /* CM2.IVAHD_CM2 register offsets */
[all …]
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| D | cm_common.c | 34 /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
41 * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
43 * @cm2: CM2 base virtual address (if present on the booted SoC)
47 void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2) in omap2_set_globals_cm() argument
50 cm2_base.va = cm2; in omap2_set_globals_cm()
293 { .compatible = "ti,omap4-cm2", .data = &cm2_data },
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| D | cm44xx.h | 10 * OMAP4 has two separate CM blocks, CM1 and CM2. This file contains
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| D | prcm44xx.h | 11 * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
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| D | cm.h | 29 extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
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| D | cm2_54xx.h | 3 * OMAP54xx CM2 instance offset macros
21 /* CM2 base address */
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| D | cm2_7xx.h | 3 * DRA7xx CM2 instance offset macros
22 /* CM2 base address */
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | cm2_44xx.h | 3 * OMAP44xx CM2 instance offset macros
25 /* CM2 base address */
31 /* CM2 instances */
44 /* CM2 clockdomain register offsets (from instance start) */
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| D | cm2_54xx.h | 3 * OMAP54xx CM2 instance offset macros
21 /* CM2 base address */
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| D | cm2_7xx.h | 3 * DRA7xx CM2 instance offset macros
22 /* CM2 base address */
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| D | cm44xx.h | 10 * OMAP4 has two separate CM blocks, CM1 and CM2. This file contains
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| D | prcm44xx.h | 11 * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
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| D | cm_common.c | 34 /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
280 { .compatible = "ti,omap4-cm2", .data = &cm2_data },
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/omap/ |
| D | prcm.txt | 19 "ti,omap4-cm2"
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/omap/ |
| D | prcm.txt | 19 "ti,omap4-cm2"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | ti-clkctrl.txt | 31 &cm2 {
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/ |
| D | baikal,bt1-l2-ctl.yaml | 15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | baikal,bt1-l2-ctl.yaml | 15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | ti-clkctrl.txt | 32 &cm2 {
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3566-soquartz-blade.dts | 86 * i2c4 is exposed on CM2 / Module1B - to PI40
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| D | rk3566-soquartz-cm4.dts | 90 * i2c4 is exposed on CM2 / Module1B - to PI40
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| D | rk3566-soquartz-model-a.dts | 113 * i2c4 is exposed on CM2 / Module1B - to PI40
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| /kernel/linux/linux-5.10/drivers/memory/ |
| D | Kconfig | 70 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
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| D | bt1-l2-ctl.c | 8 * Baikal-T1 CM2 L2-cache Control Block driver.
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| /kernel/linux/linux-6.6/drivers/memory/ |
| D | Kconfig | 68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
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