| /kernel/linux/linux-6.6/arch/alpha/kernel/ |
| D | sys_marvel.c | 96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
98 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl()
196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi()
202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
217 io7->csrs->PO7_MSI_CTL[which].csr = val; in io7_redirect_one_msi()
219 io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
228 io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14); in init_one_io7_lsi()
230 io7->csrs->PO7_LSI_CTL[which].csr; in init_one_io7_lsi()
[all …]
|
| D | core_marvel.c | 174 io7_ioport_csrs *csrs; in io7_clear_errors() local
182 csrs = IO7_CSRS_KERN(io7->pe, port); in io7_clear_errors()
184 csrs->POx_ERR_SUM.csr = -1UL; in io7_clear_errors()
185 csrs->POx_TLB_ERR.csr = -1UL; in io7_clear_errors()
186 csrs->POx_SPL_COMPLT.csr = -1UL; in io7_clear_errors()
187 csrs->POx_TRANS_SUM.csr = -1UL; in io7_clear_errors()
211 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port); in io7_init_hose() local
227 io7_port->csrs = csrs; in io7_init_hose()
268 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr; in io7_init_hose()
269 io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr; in io7_init_hose()
[all …]
|
| D | err_marvel.c | 818 err_sum |= io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
822 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error()
843 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr; in marvel_find_io7_with_error()
844 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr; in marvel_find_io7_with_error()
845 io->io7_uph = io7->csrs->IO7_UPH.csr; in marvel_find_io7_with_error()
846 io->hpi_ctl = io7->csrs->HPI_CTL.csr; in marvel_find_io7_with_error()
847 io->crd_ctl = io7->csrs->CRD_CTL.csr; in marvel_find_io7_with_error()
848 io->hei_ctl = io7->csrs->HEI_CTL.csr; in marvel_find_io7_with_error()
849 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
850 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr; in marvel_find_io7_with_error()
[all …]
|
| /kernel/linux/linux-5.10/arch/alpha/kernel/ |
| D | sys_marvel.c | 96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
98 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl()
196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi()
202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
217 io7->csrs->PO7_MSI_CTL[which].csr = val; in io7_redirect_one_msi()
219 io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
228 io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14); in init_one_io7_lsi()
230 io7->csrs->PO7_LSI_CTL[which].csr; in init_one_io7_lsi()
[all …]
|
| D | core_marvel.c | 174 io7_ioport_csrs *csrs; in io7_clear_errors() local
182 csrs = IO7_CSRS_KERN(io7->pe, port); in io7_clear_errors()
184 csrs->POx_ERR_SUM.csr = -1UL; in io7_clear_errors()
185 csrs->POx_TLB_ERR.csr = -1UL; in io7_clear_errors()
186 csrs->POx_SPL_COMPLT.csr = -1UL; in io7_clear_errors()
187 csrs->POx_TRANS_SUM.csr = -1UL; in io7_clear_errors()
211 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port); in io7_init_hose() local
227 io7_port->csrs = csrs; in io7_init_hose()
268 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr; in io7_init_hose()
269 io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr; in io7_init_hose()
[all …]
|
| D | err_marvel.c | 818 err_sum |= io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
822 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error()
843 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr; in marvel_find_io7_with_error()
844 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr; in marvel_find_io7_with_error()
845 io->io7_uph = io7->csrs->IO7_UPH.csr; in marvel_find_io7_with_error()
846 io->hpi_ctl = io7->csrs->HPI_CTL.csr; in marvel_find_io7_with_error()
847 io->crd_ctl = io7->csrs->CRD_CTL.csr; in marvel_find_io7_with_error()
848 io->hei_ctl = io7->csrs->HEI_CTL.csr; in marvel_find_io7_with_error()
849 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
850 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr; in marvel_find_io7_with_error()
[all …]
|
| /kernel/linux/linux-5.10/arch/loongarch/kvm/ |
| D | kvmcsr.h | 27 csr->csrs[gid] = gcsr_read(gid); in kvm_save_hw_gcsr()
32 gcsr_write(csr->csrs[gid], gid); in kvm_restore_hw_gcsr()
37 return csr->csrs[gid]; in kvm_read_sw_gcsr()
42 csr->csrs[gid] = val; in kvm_write_sw_gcsr()
47 csr->csrs[gid] |= val; in kvm_set_sw_gcsr()
54 csr->csrs[gid] &= ~_mask; in kvm_change_sw_gcsr()
55 csr->csrs[gid] |= val & _mask; in kvm_change_sw_gcsr()
|
| /kernel/linux/linux-5.10/arch/riscv/lib/ |
| D | uaccess.S | 20 csrs CSR_STATUS, t6
76 csrs CSR_STATUS, t6
119 csrs CSR_STATUS, t6
123 csrs CSR_STATUS, t6
|
| /kernel/linux/linux-6.6/arch/alpha/include/asm/ |
| D | core_t2.h | 68 /* The CSRs below are T3/T4 only */
95 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
99 * | CPU 0 CSRs |
101 * | CPU 1 CSRs |
103 * | CPU 2 CSRs |
105 * | CPU 3 CSRs |
111 * | Mem 0 CSRs |
113 * | Mem 1 CSRs |
115 * | Mem 2 CSRs |
117 * | Mem 3 CSRs |
[all …]
|
| /kernel/linux/linux-5.10/arch/alpha/include/asm/ |
| D | core_t2.h | 68 /* The CSRs below are T3/T4 only */
95 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
99 * | CPU 0 CSRs |
101 * | CPU 1 CSRs |
103 * | CPU 2 CSRs |
105 * | CPU 3 CSRs |
111 * | Mem 0 CSRs |
113 * | Mem 1 CSRs |
115 * | Mem 2 CSRs |
117 * | Mem 3 CSRs |
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 4 RISC-V cores include Control Status Registers (CSRs) which are local to each
6 Some of these CSRs are used to control local interrupts connected to the core.
40 definition of the hart whose CSRs control these local interrupts.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 4 RISC-V cores include Control Status Registers (CSRs) which are local to each
6 Some of these CSRs are used to control local interrupts connected to the core.
40 definition of the hart whose CSRs control these local interrupts.
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-ep.yaml | 47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
73 set of viewport CSRs mapped into the PL space. Note iATU is
79 CSRs mapped in a non-standard base address. The registers offset
86 PCS and PHY CSRs accessible over a dedicated memory mapped
|
| D | snps,dw-pcie.yaml | 56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
82 set of viewport CSRs mapped into the PL space. Note iATU is
88 CSRs mapped in a non-standard base address. The registers offset
95 PCS and PHY CSRs accessible over a dedicated memory mapped
|
| /kernel/linux/linux-6.6/arch/riscv/kernel/ |
| D | suspend.c | 55 /* Save additional CSRs*/ in cpu_suspend()
83 /* Restore additional CSRs */ in cpu_suspend()
|
| D | suspend_entry.S | 45 /* Save CSRs */
87 /* Restore CSRs */
|
| D | fpu.S | 26 csrs CSR_STATUS, t1
70 csrs CSR_STATUS, t1
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | litex.h | 4 * helper functions for accessing CSRs.
34 * means that only larger-than-32-bit CSRs will be split across multiple
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| D | nfp_arm.h | 145 /* Gasket CSRs */
151 /* BAR CSRs
210 /* MP Core CSRs */
213 /* PL320 CSRs */
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| D | nfp_arm.h | 145 /* Gasket CSRs */
151 /* BAR CSRs
210 /* MP Core CSRs */
213 /* PL320 CSRs */
|
| /kernel/linux/linux-5.10/arch/riscv/kernel/ |
| D | fpu.S | 26 csrs CSR_STATUS, t1
70 csrs CSR_STATUS, t1
|
| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-designware.h | 131 * iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each
132 * iATU region CSRs had been indirectly accessible by means of the dedicated
133 * viewport selector. The iATU/eDMA CSRs space was re-designed in DWC PCIe
135 * iATU/eDMA CSRs space.
173 * eDMA CSRs. DW PCIe IP-core v4.70a and older had the eDMA registers accessible
|
| /kernel/linux/linux-6.6/arch/riscv/kvm/ |
| D | vcpu_switch.S | 242 csrs CSR_SSTATUS, t1
285 csrs CSR_SSTATUS, t1
329 csrs CSR_SSTATUS, t1
372 csrs CSR_SSTATUS, t1
|
| /kernel/liteos_m/arch/risc-v/riscv32/gcc/asm/ |
| D | soc_common.h | 89 __asm__ volatile("csrs " #reg ", %0" : : "r"(val) : "memory"); \
107 __asm__ volatile("csrs " #reg ", %0" : : "r"(val) : "memory"); \
|
| /kernel/linux/linux-6.6/drivers/infiniband/hw/hfi1/ |
| D | chip.h | 580 * per-context or per-SDMA CSRs that are not mappable to user-space.
586 /* kernel per-context CSRs are separated by 0x100 */ in read_kctxt_csr()
593 /* kernel per-context CSRs are separated by 0x100 */ in write_kctxt_csr()
614 * per-context CSRs that are mappable to user space. All these CSRs
616 * different processes without exposing other contexts' CSRs
621 /* user per-context CSRs are separated by 0x1000 */ in read_uctxt_csr()
628 /* user per-context CSRs are separated by 0x1000 */ in write_uctxt_csr()
|