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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
D	pmu.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Mark Rutland <mark.rutland@arm.com> 11 - Will Deacon <will.deacon@arm.com> 14 ARM cores often have a PMU for counting cpu and cache events like cache misses 16 representation in the device tree should be done as under:- 21 - enum: 22 - apm,potenza-pmu 23 - apple,avalanche-pmu [all …]`
D	cpus.yaml	1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 59 On 32-bit ARM v7 or later systems this property is 68 On ARM v8 64-bit systems this property is required [all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
D	pmu.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Mark Rutland <mark.rutland@arm.com> 11 - Will Deacon <will.deacon@arm.com> 14 ARM cores often have a PMU for counting cpu and cache events like cache misses 16 representation in the device tree should be done as under:- 21 - enum: 22 - apm,potenza-pmu 23 - arm,armv8-pmuv3 # Only for s/w models [all …]`
D	cpus.yaml	1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 59 On 32-bit ARM v7 or later systems this property is 68 On ARM v8 64-bit systems this property is required [all …]
/kernel/linux/linux-6.6/arch/arm64/
D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0-only 260 ARM 64-bit (AArch64) Linux support. 269 depends on $(cc-option,-fpatchable-function-entry=2) 301 # VA_BITS - PAGE_SHIFT - 3 377 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 428 A/D updates can occur after a PTE has been marked invalid. 432 at stage-2. 440 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce… 445 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 448 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors [all …]
/kernel/liteos_m/
D	README_zh.md	1 # LiteOS-M内核<a name="ZH-CN_TOPIC_0000001096757661"></a> 3 - [简介](#section11660541593) 4 - [目录](#section161941989596) 5 - [约束](#section119744591305) 6 - [使用说明](#section3732185231214) 7 - [贡献](#section1371123476307) 8 - [相关仓](#section1371113476307) 10 ## 简介<a name="section11660541593"></a> 12 OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系统内核，具有小体积、低功耗、高性能的特点，其代码结构简单，主要包括内核最小功能集、内核抽象层、可选组件以及工程目录… 14 图 1 OpenHarmony LiteOS-M核内核架构图<a name="fig0865152210223"></a> [all …]
/kernel/uniproton/src/include/uapi/hw/armv7-m/
D	prt_exc.h	2 * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved. 6 * You may obtain a copy of Mulan PSL v2 at: 9 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 10 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12 * Create: 2009-12-22 109 * Cortex-MX异常具体类型:总线状态寄存器入栈时发生错误。 114 * Cortex-MX异常具体类型:总线状态寄存器出栈时发生错误。 119 * Cortex-MX异常具体类型:总线状态寄存器不精确的数据访问违例。 124 * Cortex-MX异常具体类型:总线状态寄存器精确的数据访问违例。 129 * Cortex-MX异常具体类型:总线状态寄存器取指时的访问违例。 [all …]
/kernel/liteos_m/arch/arm/
D	Kconfig	4 # ARM has 32-bit(Aarch32) and 64-bit(Aarch64) implementations 10 32-bit ARM architecture implementations, Except the M-profile. 11 It is not limited to ARMv7-A but also ARMv7-R, ARMv8-A 32-bit and etc. 27 default "armv7-m" if ARCH_ARM_V7M 28 default "armv8-m" if ARCH_ARM_V8M 48 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles. 49 …VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support co… 54 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles. 55 …VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support co… 56 …VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to … [all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2022-2023 Huawei Device Co., Ltd. All rights reserved. 20 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 44 * Highest priority of a hardware interrupt. 52 * Lowest priority of a hardware interrupt. 66 * Count of M-Core system interrupt vector. 72 * Count of M-Core interrupt vector. 83 …* The value range of the interrupt number applicable for a Cortex-M55 platformis [OS_USER_HWI_MIN… 93 * Solution: Pass in a valid non-null hardware interrupt handling function. 123 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 134 * The value range of the interrupt priority applicable for a Cortex-M55 platform is [0,15]. [all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/cpu/
D	cpu-topology.txt	`6 1 - Introduction 9 In a SMP system, the hierarchy of CPUs is defined through three entities that 12 - socket 13 - cluster 14 - core 15 - thread 18 symmetric multi-threading (SMT) is supported or not. 20 For instance in a system where CPUs support SMT, "cpu" nodes represent all 29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be 35 A topology description containing phandles to cpu nodes that are not compliant [all …]`
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpu/
D	cpu-topology.txt	`6 1 - Introduction 9 In a SMP system, the hierarchy of CPUs is defined through three entities that 12 - socket 13 - cluster 14 - core 15 - thread 18 symmetric multi-threading (SMT) is supported or not. 20 For instance in a system where CPUs support SMT, "cpu" nodes represent all 29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be 35 A topology description containing phandles to cpu nodes that are not compliant [all …]`
/kernel/liteos_m/arch/arm/cortex-m7/gcc/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 61 * Count of M-Core system interrupt vector. 67 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M7 platformis [OS_USER_HWI_MIN,… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m4/keil/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M4 platformis [OS_USER_HWI_MIN,… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m4/iar/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M4 platformis [OS_USER_HWI_MIN,… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m7/iar/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M7 platformis [OS_USER_HWI_MIN,… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m4/gcc/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m3/keil/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 47 * Highest priority of a hardware interrupt. 55 * Lowest priority of a hardware interrupt. 63 * Count of M-Core system interrupt vector. 69 * Count of M-Core interrupt vector. 92 …* The value range of the interrupt number applicable for a Cortex-M3 platform is [OS_USER_HWI_MIN,… 102 * Solution: Pass in a valid non-null hardware interrupt handling function. 132 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 45 * Highest priority of a hardware interrupt. 53 * Lowest priority of a hardware interrupt. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… [all …]
/kernel/linux/linux-6.6/Documentation/translations/zh_TW/arch/arm64/
D	silicon-errata.txt	1 SPDX-License-Identifier: GPL-2.0 3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst 6 original document maintainer directly. However, if you have a problem 9 or if there is a problem with the translation. 15 --------------------------------------------------------------------- 16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯 30 --------------------------------------------------------------------- 41 A 類：無可行補救措施的嚴重缺陷。 50 情況下，爲將 A 類缺陷當作 C 類處理，可能需要用類似的手段。這些手段被 55 相應的內核配置（Kconfig）選項被加在「內核特性（Kernel Features）」-> [all …]

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