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/kernel/linux/linux-6.6/Documentation/gpu/amdgpu/
Ddgpu-asic-info-table.csv1 Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version
3 AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
4 AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, --
5 AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --
6 AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE…
7 AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE 2 / UVD 4.2, 1
8 AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1
10 AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3
11 AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
12 …on (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 / …
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_transform.h"
41 #include "dce/dce_link_encoder.h"
42 #include "dce/dce_stream_encoder.h"
43 #include "dce/dce_audio.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_clock_source.h"
48 #include "dce/dce_hwseq.h"
50 #include "dce/dce_abm.h"
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c37 #include "dce/dce_mem_input.h"
38 #include "dce/dce_transform.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_audio.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_clock_source.h"
46 #include "dce/dce_hwseq.h"
48 #include "dce/dce_abm.h"
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c36 #include "dce/dce_audio.h"
40 #include "dce/dce_link_encoder.h"
41 #include "dce/dce_stream_encoder.h"
42 #include "dce/dce_mem_input.h"
44 #include "dce/dce_ipp.h"
45 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_hwseq.h"
52 #include "dce/dce_aux.h"
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Ddce110_opp_v.c29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
32 #include "dce/dce_opp.h"
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c34 #include "dce/dce_audio.h"
38 #include "dce/dce_link_encoder.h"
39 #include "dce/dce_stream_encoder.h"
40 #include "dce/dce_mem_input.h"
42 #include "dce/dce_ipp.h"
43 #include "dce/dce_transform.h"
45 #include "dce/dce_opp.h"
47 #include "dce/dce_clock_source.h"
48 #include "dce/dce_hwseq.h"
50 #include "dce/dce_aux.h"
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Ddce110_opp_v.c29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
32 #include "dce/dce_opp.h"
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
204 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
210 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
223 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_dio_link_encoder.c124 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn301_link_encoder_construct()
129 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn301_link_encoder_construct()
130 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn301_link_encoder_construct()
131 * By this, adding DIGG should not hurt DCE 8.0. in dcn301_link_encoder_construct()
132 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn301_link_encoder_construct()
174 /* Override features with DCE-specific values */ in dcn301_link_encoder_construct()
/kernel/linux/linux-5.10/include/uapi/linux/hdlc/
Dioctl.h10 #define CLOCK_INT 2 /* Internal TX and RX clock - DCE */
65 unsigned short dce; /* 1 for DCE (network side) operation */ member
83 unsigned short dce; /* 1 for DCE (network side) operation */ member
/kernel/linux/linux-6.6/include/uapi/linux/hdlc/
Dioctl.h10 #define CLOCK_INT 2 /* Internal TX and RX clock - DCE */
65 unsigned short dce; /* 1 for DCE (network side) operation */ member
83 unsigned short dce; /* 1 for DCE (network side) operation */ member
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
DMakefile23 # Makefile for common 'dce' logic
29 DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ macro
35 AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
Ddce_clk_mgr.c54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
202 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS in get_max_pixel_clock_for_all_paths()
227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
460 * the dce clock manager. This operation will overwrite the existing dprefclk
615 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
617 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
619 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_link_encoder.c156 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn201_link_encoder_construct()
161 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn201_link_encoder_construct()
162 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn201_link_encoder_construct()
163 * By this, adding DIGG should not hurt DCE 8.0. in dcn201_link_encoder_construct()
164 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn201_link_encoder_construct()
191 /* Override features with DCE-specific values */ in dcn201_link_encoder_construct()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
DMakefile23 # Makefile for common 'dce' logic
29 DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ macro
35 AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
Ddce_clk_mgr.c54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
202 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS in get_max_pixel_clock_for_all_paths()
227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
464 * the dce clock manager. This operation will overwrite the existing dprefclk
619 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
625 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
627 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_resource.c39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_mem_input.h"
42 #include "dce/dce_ipp.h"
43 #include "dce/dce_transform.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_clock_source.h"
46 #include "dce/dce_audio.h"
47 #include "dce/dce_hwseq.h"
49 #include "dce/dce_panel_cntl.h"
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_resource.c37 #include "dce/dce_link_encoder.h"
38 #include "dce/dce_stream_encoder.h"
39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_ipp.h"
41 #include "dce/dce_transform.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_clock_source.h"
44 #include "dce/dce_audio.h"
45 #include "dce/dce_hwseq.h"
47 #include "dce/dce_panel_cntl.h"
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/kernel/linux/linux-5.10/drivers/tty/serial/
Dicom.h70 u8 dce_resvd[20]; /* 1C8-1DB DCE Rsvd */
71 u8 dce_resvd21; /* 1DC DCE Rsvd (21st byte */
80 u8 dce_command; /* 1E7 dce command reg */
81 u8 dce_cmd_status; /* 1E8 dce command stat */
82 u8 x21_r1_ioff; /* 1E9 dce ready counter */
83 u8 x21_r0_ioff; /* 1EA dce not ready ctr */
84 u8 x21_ralt_ioff; /* 1EB dce CNR counter */
85 u8 x21_r1_ion; /* 1EC dce ready I on ctr */
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_link_encoder.c137 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn30_link_encoder_construct()
142 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn30_link_encoder_construct()
143 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn30_link_encoder_construct()
144 * By this, adding DIGG should not hurt DCE 8.0. in dcn30_link_encoder_construct()
145 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn30_link_encoder_construct()
187 /* Override features with DCE-specific values */ in dcn30_link_encoder_construct()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_link_encoder.c138 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn30_link_encoder_construct()
143 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn30_link_encoder_construct()
144 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn30_link_encoder_construct()
145 * By this, adding DIGG should not hurt DCE 8.0. in dcn30_link_encoder_construct()
146 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn30_link_encoder_construct()
188 /* Override features with DCE-specific values */ in dcn30_link_encoder_construct()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_link_encoder.c376 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn21_link_encoder_construct()
381 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn21_link_encoder_construct()
382 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn21_link_encoder_construct()
383 * By this, adding DIGG should not hurt DCE 8.0. in dcn21_link_encoder_construct()
384 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn21_link_encoder_construct()
426 /* Override features with DCE-specific values */ in dcn21_link_encoder_construct()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_resource.c28 #include "dce/dce_8_0_d.h"
29 #include "dce/dce_8_0_sh_mask.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_resource.c28 #include "dce/dce_6_0_d.h"
29 #include "dce/dce_6_0_sh_mask.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
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