| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | mmci.txt | 11 - compatible : contains "arm,pl18x", "arm,primecell".
12 - vmmc-supply : phandle to the regulator device tree node, mentioned
16 - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides
18 - resets : phandle to internal reset line.
20 - vqmmc-supply : phandle to the regulator device tree node, mentioned
23 - st,sig-dir-dat0 : bus signal direction pin used for DAT[0].
24 - st,sig-dir-dat2 : bus signal direction pin used for DAT[2].
25 - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1].
26 - st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7].
27 - st,sig-dir-cmd : cmd signal direction pin used for CMD.
[all …]
|
| /kernel/linux/linux-5.10/drivers/ata/ |
| D | pata_ali.c | 2 * pata_ali.c - ALI 15x3 PATA for new ATA layer
8 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
9 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
10 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
12 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
22 * otherwise should do atapi DMA (For now for old we do PIO only for
42 MODULE_PARM_DESC(atapi_dma, "Enable ATAPI DMA (0=disable, 1=enable)");
54 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
55 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
59 .ident = "Toshiba Satellite S1800-814",
[all …]
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| D | ahci.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
81 HOST_RESET = BIT(0), /* reset controller; self-clear */
90 HOST_CAP_PART = BIT(13), /* Partial state capable */
91 HOST_CAP_SSC = BIT(14), /* Slumber state capable */
93 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
99 HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
[all …]
|
| /kernel/linux/linux-6.6/drivers/ata/ |
| D | pata_ali.c | 2 * pata_ali.c - ALI 15x3 PATA for new ATA layer
8 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
9 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
10 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
12 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
22 * otherwise should do atapi DMA (For now for old we do PIO only for
42 MODULE_PARM_DESC(atapi_dma, "Enable ATAPI DMA (0=disable, 1=enable)");
54 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
55 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
59 .ident = "Toshiba Satellite S1800-814",
[all …]
|
| D | ahci.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
80 HOST_RESET = BIT(0), /* reset controller; self-clear */
89 HOST_CAP_PART = BIT(13), /* Partial state capable */
90 HOST_CAP_SSC = BIT(14), /* Slumber state capable */
92 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
98 HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/ |
| D | owl-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S900 SoC variants.
15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 - $ref: dma-controller.yaml#
[all …]
|
| D | socionext,uniphier-xdmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier external DMA controller
10 This describes the devicetree bindings for an external DMA engine to perform
11 memory-to-memory or peripheral-to-memory data transfer capable of supporting
15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
18 - $ref: dma-controller.yaml#
22 const: socionext,uniphier-xdmac
[all …]
|
| D | mv-xor-v2.txt | 4 - compatible: one of the following values:
5 "marvell,armada-7k-xor"
6 "marvell,xor-v2"
7 - reg: Should contain registers location and length (two sets)
8 the first set is the DMA registers
10 - msi-parent: Phandle to the MSI-capable interrupt controller used for
14 - clocks: Optional reference to the clocks used by the XOR engine.
15 - clock-names: mandatory if there is a second clock, in this case the
23 compatible = "marvell,xor-v2";
26 msi-parent = <&gic_v2m0>;
[all …]
|
| D | st_fdma.txt | 3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
[all …]
|
| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | owl-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 - $ref: "dma-controller.yaml#"
23 - actions,s900-dma
[all …]
|
| D | socionext,uniphier-xdmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier external DMA controller
10 This describes the devicetree bindings for an external DMA engine to perform
11 memory-to-memory or peripheral-to-memory data transfer capable of supporting
15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
18 - $ref: "dma-controller.yaml#"
22 const: socionext,uniphier-xdmac
[all …]
|
| D | renesas,shdma.txt | 3 Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
4 instances, capable of serving any of a common set of DMA slave devices, using
6 SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
7 DMAC instances have the same number of channels and use the same DMA
8 descriptors. Therefore respective DMA DT bindings can also all be placed in the
12 * DMA multiplexer
15 - compatible: should be "renesas,shdma-mux"
16 - #dma-cells: should be <1>, see "dmas" property below
19 - dma-channels: number of DMA channels
20 - dma-requests: number of DMA request signals
[all …]
|
| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller bindings
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
[all …]
|
| D | mv-xor-v2.txt | 4 - compatible: one of the following values:
5 "marvell,armada-7k-xor"
6 "marvell,xor-v2"
7 - reg: Should contain registers location and length (two sets)
8 the first set is the DMA registers
10 - msi-parent: Phandle to the MSI-capable interrupt controller used for
14 - clocks: Optional reference to the clocks used by the XOR engine.
15 - clock-names: mandatory if there is a second clock, in this case the
23 compatible = "marvell,xor-v2";
26 msi-parent = <&gic_v2m0>;
[all …]
|
| D | st_fdma.txt | 3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
[all …]
|
| /kernel/linux/linux-6.6/arch/xtensa/include/asm/ |
| D | dma.h | 2 * include/asm-xtensa/dma.h
8 * Copyright (C) 2003 - 2005 Tensilica Inc.
17 * This is only to be defined if we have PC-like DMA.
28 * The maximum virtual address to which DMA transfers
31 * NOTE: This is board (platform) specific, not processor-specific!
33 * NOTE: This assumes DMA transfers can only be performed on
36 * means the maximum possible size of this DMA area is
40 * NOTE: When the entire KSEG area is DMA capable, we subtract
48 #define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KIO_SIZE - 1)
51 /* Reserve and release a DMA channel */
|
| /kernel/linux/linux-5.10/arch/xtensa/include/asm/ |
| D | dma.h | 2 * include/asm-xtensa/dma.h
8 * Copyright (C) 2003 - 2005 Tensilica Inc.
17 * This is only to be defined if we have PC-like DMA.
28 * The maximum virtual address to which DMA transfers
31 * NOTE: This is board (platform) specific, not processor-specific!
33 * NOTE: This assumes DMA transfers can only be performed on
36 * means the maximum possible size of this DMA area is
40 * NOTE: When the entire KSEG area is DMA capable, we subtract
48 #define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KIO_SIZE - 1)
51 /* Reserve and release a DMA channel */
|
| /kernel/linux/linux-5.10/drivers/acpi/arm64/ |
| D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/dma-direct.h>
15 * If @dev is expected to be DMA-capable then the bus code that created in acpi_arch_dma_setup()
20 if (!dev->dma_mask) { in acpi_arch_dma_setup()
21 dev_warn(dev, "DMA mask not set\n"); in acpi_arch_dma_setup()
22 dev->dma_mask = &dev->coherent_dma_mask; in acpi_arch_dma_setup()
25 if (dev->coherent_dma_mask) in acpi_arch_dma_setup()
26 size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1); in acpi_arch_dma_setup()
34 for (end = 0; r->size; r++) { in acpi_arch_dma_setup()
35 if (r->dma_start + r->size - 1 > end) in acpi_arch_dma_setup()
[all …]
|
| /kernel/linux/linux-6.6/drivers/acpi/arm64/ |
| D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/dma-direct.h>
15 * If @dev is expected to be DMA-capable then the bus code that created in acpi_arch_dma_setup()
20 if (!dev->dma_mask) { in acpi_arch_dma_setup()
21 dev_warn(dev, "DMA mask not set\n"); in acpi_arch_dma_setup()
22 dev->dma_mask = &dev->coherent_dma_mask; in acpi_arch_dma_setup()
25 if (dev->coherent_dma_mask) in acpi_arch_dma_setup()
26 size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1); in acpi_arch_dma_setup()
34 for (end = 0; r->size; r++) { in acpi_arch_dma_setup()
35 if (r->dma_start + r->size - 1 > end) in acpi_arch_dma_setup()
[all …]
|
| /kernel/linux/linux-5.10/include/uapi/linux/ |
| D | rio_mport_cdev.h | 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
3 * Copyright (c) 2015-2016, Integrated Device Technology Inc.
11 * License(GPL) Version 2, or the BSD-3 Clause license below:
57 * - memory mapped (MAPPED)
58 * - packet generation from memory (TRANSFER)
83 __u32 cap_sys_size; /* Capable system sizes */
84 __u32 cap_addr_size; /* Capable addressing sizes */
85 __u32 cap_transfer_mode; /* Capable transfer modes */
91 * - incoming port-writes
92 * - incoming doorbells
[all …]
|
| /kernel/linux/linux-6.6/include/uapi/linux/ |
| D | rio_mport_cdev.h | 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
3 * Copyright (c) 2015-2016, Integrated Device Technology Inc.
11 * License(GPL) Version 2, or the BSD-3 Clause license below:
57 * - memory mapped (MAPPED)
58 * - packet generation from memory (TRANSFER)
83 __u32 cap_sys_size; /* Capable system sizes */
84 __u32 cap_addr_size; /* Capable addressing sizes */
85 __u32 cap_transfer_mode; /* Capable transfer modes */
91 * - incoming port-writes
92 * - incoming doorbells
[all …]
|
| /kernel/linux/linux-5.10/Documentation/i2c/ |
| D | dma-considerations.rst | 2 Linux I2C and DMA
5 Given that I2C is a low-speed bus, over which the majority of messages
6 transferred are small, it is not considered a prime user of DMA access. At this
7 time of writing, only 10% of I2C bus master drivers have DMA support
9 DMA for it will likely add more overhead than a plain PIO transfer.
11 Therefore, it is *not* mandatory that the buffer of an I2C message is DMA safe.
13 rarely used. However, it is recommended to use a DMA-safe buffer if your
14 message size is likely applicable for DMA. Most drivers have this threshold
18 I2C bus master driver is using USB as a bridge, then you need to have DMA
22 -------
[all …]
|
| /kernel/linux/linux-6.6/Documentation/i2c/ |
| D | dma-considerations.rst | 2 Linux I2C and DMA
5 Given that I2C is a low-speed bus, over which the majority of messages
6 transferred are small, it is not considered a prime user of DMA access. At this
7 time of writing, only 10% of I2C bus master drivers have DMA support
9 DMA for it will likely add more overhead than a plain PIO transfer.
11 Therefore, it is *not* mandatory that the buffer of an I2C message is DMA safe.
13 rarely used. However, it is recommended to use a DMA-safe buffer if your
14 message size is likely applicable for DMA. Most drivers have this threshold
18 I2C bus master driver is using USB as a bridge, then you need to have DMA
22 -------
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra210-admaif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^admaif@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-admaif
28 - nvidia,tegra186-admaif
[all …]
|