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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
31 While ECAM extends this by 4 bits to accommodate 4k of function space:
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Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
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Dpcie-al.txt3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
5 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
9 - compatible:
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
16 - reg:
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
21 - reg-names:
25 - "config" PCIe ECAM space
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
31 While ECAM extends this by 4 bits to accommodate 4k of function space:
[all …]
Dpcie-al.txt3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
5 Documentation/devicetree/bindings/pci/designware-pcie.txt.
9 - compatible:
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
16 - reg:
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
21 - reg-names:
25 - "config" PCIe ECAM space
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/kernel/linux/linux-5.10/include/linux/
Dpci-ecam.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * use ECAM.
34 void __iomem *win; /* 64-bit single mapping */
35 void __iomem **winp; /* 32-bit per-bus mapping */
37 struct device *parent;/* ECAM res was from this dev */
46 /* map_bus when ->sysdata is an instance of pci_config_window */
49 /* default ECAM ops */
53 extern const struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
54 extern const struct pci_ecam_ops pci_32b_read_ops; /* 32-bit read only */
58 extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
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/kernel/linux/linux-6.6/include/linux/
Dpci-ecam.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * Memory address shift values for the byte-level address that
18 * Enhanced Configuration Access Mechanism (ECAM)
21 * Section 7.2.2, Table 7-1, p. 677.
53 * use ECAM.
62 void __iomem *win; /* 64-bit single mapping */
63 void __iomem **winp; /* 32-bit per-bus mapping */
65 struct device *parent;/* ECAM res was from this dev */
74 /* map_bus when ->sysdata is an instance of pci_config_window */
77 /* default ECAM ops */
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/kernel/linux/linux-5.10/drivers/pci/controller/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
50 bool "Renesas R-Car Gen2 Internal PCI controller"
54 Say Y here if you want internal PCI support on R-Car Gen2 SoC.
56 built-in EHCI/OHCI host controller present on each one.
59 bool "Renesas R-Car PCIe controller"
64 Say Y here if you want PCIe controller support on R-Car SoCs.
68 bool "Renesas R-Car PCIe host controller"
73 Say Y here if you want PCIe controller support on R-Car SoCs in host
77 bool "Renesas R-Car PCIe endpoint controller"
81 Say Y here if you want PCIe controller support on R-Car SoCs in
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Dpcie-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
89 /* ECAM definitions */
97 * struct xilinx_pcie_port - PCIe port information
120 return readl(port->reg_base + reg); in pcie_read()
125 writel(val, port->reg_base + reg); in pcie_write()
135 * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
140 struct device *dev = port->dev; in xilinx_pcie_clear_err_interrupts()
152 * xilinx_pcie_valid_device - Check if a valid device is present on bus
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Dpcie-xilinx-nwl.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
32 /* Egress - Bridge translation registers */
42 /* Ingress - address translations */
50 /* Rxed msg fifo - Interrupt status registers */
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
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Dpci-xgene.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
77 return readl(port->csr_base + reg); in xgene_pcie_readl()
82 writel(val, port->csr_base + reg); in xgene_pcie_writel()
95 return (struct xgene_pcie_port *)(bus->sysdata); in pcie_bus_to_port()
97 cfg = bus->sysdata; in pcie_bus_to_port()
98 return (struct xgene_pcie_port *)(cfg->priv); in pcie_bus_to_port()
109 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
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/kernel/linux/linux-6.6/drivers/pci/controller/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
45 system-on-chips, like the Apple M1. This is required for the USB
46 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
63 Broadcom STB based SoCs, like the Raspberry Pi 4.
102 bool "Cavium Thunder PCIe controller to off-chip devices"
110 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
115 Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
149 in the Intel IXP4xx XScale-based network processor SoC.
185 is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370,
205 multi-function devices.
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Dpcie-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
24 #include <linux/pci-ecam.h>
94 * struct xilinx_pcie - PCIe port information
115 return readl(pcie->reg_base + reg); in pcie_read()
120 writel(val, pcie->reg_base + reg); in pcie_write()
130 * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
135 struct device *dev = pcie->dev; in xilinx_pcie_clear_err_interrupts()
147 * xilinx_pcie_valid_device - Check if a valid device is present on bus
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Dpcie-xilinx-nwl.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
21 #include <linux/pci-ecam.h>
33 /* Egress - Bridge translation registers */
43 /* Ingress - address translations */
51 /* Rxed msg fifo - Interrupt status registers */
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
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Dpci-xgene.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
19 #include <linux/pci-acpi.h>
20 #include <linux/pci-ecam.h>
74 return readl(port->csr_base + reg); in xgene_pcie_readl()
79 writel(val, port->csr_base + reg); in xgene_pcie_writel()
92 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port()
94 cfg = bus->sysdata; in pcie_bus_to_port()
95 return (struct xgene_pcie *)(cfg->priv); in pcie_bus_to_port()
106 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
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Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
150 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
159 * @imap_addr_offset: register offset between the upper and lower 32-bit
400 struct iproc_pcie *pcie = bus->sysdata; in iproc_data()
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Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
140 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
295 writel(val, pcie->base + reg); in advk_writel()
300 return readl(pcie->base + reg); in advk_readl()
315 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
323 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
337 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_training()
360 return -ETIMEDOUT; in advk_pcie_wait_for_link()
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Dpci-hyperv.c1 // SPDX-License-Identifier: GPL-2.0
8 * This driver acts as a paravirtual front-end for PCI Express root buses.
9 * When a PCI Express function (either an entire device or an SR-IOV
13 * VM within Hyper-V, there may seem to be no PCI bus at all in the VM
18 * to the VM using this front-end will appear at "device 0", the domain will
24 * MSI or MSI-X) associated with the functions on the bus. As interrupts are
28 * vector. This driver does not support level-triggered (line-based)
32 * The rest of this driver mostly maps PCI concepts onto underlying Hyper-V
34 * by Hyper-V is mapped into a single page of memory space, and the
37 * the PCI back-end driver in Hyper-V.
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Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
256 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
378 writel(value, pcie->afi + offset); in afi_writel()
383 return readl(pcie->afi + offset); in afi_readl()
389 writel(value, pcie->pads + offset); in pads_writel()
394 return readl(pcie->pads + offset); in pads_readl()
398 * The configuration space mapping on Tegra is somewhat similar to the ECAM
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/kernel/linux/linux-5.10/arch/x86/pci/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Low-Level PCI Support for PC
5 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
10 #include <linux/pci-acpi.h>
35 int pcibios_last_bus = -1;
44 return raw_pci_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
46 return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
47 return -EINVAL; in raw_pci_read()
54 return raw_pci_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
56 return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
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/kernel/linux/linux-6.6/arch/x86/pci/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Low-Level PCI Support for PC
5 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
10 #include <linux/pci-acpi.h>
35 int pcibios_last_bus = -1;
44 return raw_pci_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
46 return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
47 return -EINVAL; in raw_pci_read()
54 return raw_pci_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
56 return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/hisilicon/
Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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