| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | am335x-boneblack.dts | 65 "P8_25 [emmc]",
66 "[emmc]",
67 "P8_5 [emmc]",
68 "P8_6 [emmc]",
69 "P8_23 [emmc]",
70 "P8_22 [emmc]",
71 "P8_3 [emmc]",
72 "P8_4 [emmc]",
85 "[emmc]",
95 "P8_21 [emmc]",
[all …]
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| D | meson8b-ec100.dts | 30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
386 "NAND_D0 (EMMC)", "NAND_D1 (EMMC)",
387 "NAND_D2 (EMMC)", "NAND_D3 (EMMC)",
388 "NAND_D4 (EMMC)", "NAND_D5 (EMMC)",
389 "NAND_D6 (EMMC)", "NAND_D7 (EMMC)",
390 "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)",
391 "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)",
392 "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)",
393 "nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS",
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| D | sun7i-a20-olimex-som204-evb-emmc.dts | 3 * Device Tree Source for A20-SOM204-EVB-eMMC Board
13 model = "Olimex A20-SOM204-EVB-eMMC";
14 compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
17 compatible = "mmc-pwrseq-emmc";
29 emmc: emmc@0 { label
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| D | sun7i-a20-olimex-som-evb-emmc.dts | 3 * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board
14 model = "Olimex A20-Olimex-SOM-EVB-eMMC";
15 compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
18 compatible = "mmc-pwrseq-emmc";
30 emmc: emmc@0 { label
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | intel,lgm-emmc-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
7 title: Intel Lightning Mountain(LGM) eMMC PHY
13 Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
14 node is used to reference the base address of eMMC phy registers.
16 The eMMC PHY node should be the child of a syscon node with the
27 - intel,lgm-emmc-phy
28 - intel,keembay-emmc-phy
59 emmc_phy: emmc-phy@a8 {
60 compatible = "intel,lgm-emmc-phy";
62 clocks = <&emmc>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | intel,lgm-emmc-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
7 title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings
13 Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
14 node is used to reference the base address of eMMC phy registers.
16 The eMMC PHY node should be the child of a syscon node with the
27 - const: intel,lgm-emmc-phy
28 - const: intel,keembay-emmc-phy
59 emmc_phy: emmc-phy@a8 {
60 compatible = "intel,lgm-emmc-phy";
62 clocks = <&emmc>;
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/ |
| D | allwinner,sun4i-a10-mmc.yaml | 25 - const: allwinner,sun8i-a83t-emmc
28 - const: allwinner,sun50i-a64-emmc
30 - const: allwinner,sun50i-a100-emmc
36 - const: allwinner,sun8i-r40-emmc
37 - const: allwinner,sun50i-a64-emmc
42 - const: allwinner,sun50i-h5-emmc
43 - const: allwinner,sun50i-a64-emmc
48 - const: allwinner,sun50i-h6-emmc
49 - const: allwinner,sun50i-a64-emmc
54 - const: allwinner,sun20i-d1-emmc
[all …]
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| D | mmc-pwrseq-emmc.yaml | 4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
7 title: Simple eMMC hardware reset provider
13 The purpose of this driver is to perform standard eMMC hw reset
16 fix possible issues if bootloader has left eMMC card in initialized or
19 doesn't have hardware reset logic connected to emmc card and (limited or
20 broken) ROM bootloaders are unable to read second stage from the emmc
25 const: mmc-pwrseq-emmc
31 and then deasserted to perform eMMC card reset. To perform
45 compatible = "mmc-pwrseq-emmc";
|
| D | marvell,xenon-sdhci.yaml | 74 - emmc 5.1 phy
75 - emmc 5.0 phy
77 Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
78 marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
79 choice if this property is not provided. To select eMMC 5.0 PHY, set:
80 marvell,xenon-phy-type = "emmc 5.0 phy"
82 All those types of PHYs can support eMMC, SD and SDIO. Please note that
84 entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean
85 that this Xenon SDHC only supports eMMC 5.1.
94 Only available for eMMC PHY.
[all …]
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| D | mmc-controller.yaml | 50 Non-removable slot (like eMMC); assume always present.
93 - for eMMC, the maximum supported frequency is 200MHz,
112 line. Not used in combination with eMMC or SDIO.
173 eMMC hardware reset is supported
193 eMMC high-speed DDR mode (1.2V I/O) is supported.
198 eMMC high-speed DDR mode (1.8V I/O) is supported.
203 eMMC high-speed DDR mode (3.3V I/O) is supported.
208 eMMC HS200 mode (1.2V I/O) is supported.
213 eMMC HS200 mode (1.8V I/O) is supported.
218 eMMC HS400 mode (1.2V I/O) is supported.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | mmc-pwrseq-emmc.yaml | 4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
7 title: Simple eMMC hardware reset provider binding
13 The purpose of this driver is to perform standard eMMC hw reset
16 fix possible issues if bootloader has left eMMC card in initialized or
19 doesn't have hardware reset logic connected to emmc card and (limited or
20 broken) ROM bootloaders are unable to read second stage from the emmc
25 const: mmc-pwrseq-emmc
31 and then deasserted to perform eMMC card reset. To perform
45 compatible = "mmc-pwrseq-emmc";
|
| D | marvell,xenon-sdhci.txt | 46 To select eMMC 5.1 PHY, set:
47 marvell,xenon-phy-type = "emmc 5.1 phy"
48 eMMC 5.1 PHY is the default choice if this property is not provided.
49 To select eMMC 5.0 PHY, set:
50 marvell,xenon-phy-type = "emmc 5.0 phy"
52 All those types of PHYs can support eMMC, SD and SDIO.
55 For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only
56 supports eMMC 5.1.
60 Only available for eMMC PHY.
66 Only available for eMMC PHY.
[all …]
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| D | allwinner,sun4i-a10-mmc.yaml | 25 - const: allwinner,sun8i-a83t-emmc
27 - const: allwinner,sun50i-a64-emmc
33 - const: allwinner,sun8i-r40-emmc
34 - const: allwinner,sun50i-a64-emmc
39 - const: allwinner,sun50i-h5-emmc
40 - const: allwinner,sun50i-a64-emmc
45 - const: allwinner,sun50i-h6-emmc
46 - const: allwinner,sun50i-a64-emmc
|
| /kernel/linux/linux-5.10/Documentation/driver-api/mmc/ |
| D | mmc-tools.rst | 16 - Determine the eMMC writeprotect status.
17 - Set the eMMC writeprotect status.
18 - Set the eMMC data sector size to 4KB by disabling emulation.
25 - Enable the eMMC BKOPS feature.
26 - Permanently enable the eMMC H/W Reset feature.
27 - Permanently disable the eMMC H/W Reset feature.
33 - Enable the eMMC cache feature.
34 - Disable the eMMC cache feature.
|
| /kernel/linux/linux-6.6/Documentation/driver-api/mmc/ |
| D | mmc-tools.rst | 16 - Determine the eMMC writeprotect status.
17 - Set the eMMC writeprotect status.
18 - Set the eMMC data sector size to 4KB by disabling emulation.
25 - Enable the eMMC BKOPS feature.
26 - Permanently enable the eMMC H/W Reset feature.
27 - Permanently disable the eMMC H/W Reset feature.
33 - Enable the eMMC cache feature.
34 - Disable the eMMC cache feature.
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-gxl-s905x-khadas-vim.dts | 144 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
145 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
146 "eMMC Clk", "eMMC Reset", "eMMC CMD",
147 "", "BOOT_MODE", "", "", "eMMC Data Strobe",
|
| D | meson-gxl-s905x-libretech-cc.dts | 46 emmc_pwrseq: emmc-pwrseq {
47 compatible = "mmc-pwrseq-emmc";
127 /* This is provided by LDOs on the eMMC daugther card */
269 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
270 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
271 "eMMC Clk", "eMMC Reset", "eMMC CMD",
272 "ALT BOOT MODE", "", "", "", "eMMC Data Strobe",
320 /* eMMC */
|
| D | meson-gxl-s805x-libretech-ac.dts | 53 emmc_pwrseq: emmc-pwrseq {
54 compatible = "mmc-pwrseq-emmc";
246 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
247 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
248 "eMMC Clk", "eMMC Reset", "eMMC CMD",
277 /* eMMC */
|
| D | meson-gxbb-nanopi-k2.dts | 106 emmc_pwrseq: emmc-pwrseq {
107 compatible = "mmc-pwrseq-emmc";
217 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
218 "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
219 "eMMC Reset", "eMMC CMD",
220 "", "", "", "", "eMMC DS",
319 /* eMMC */
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/amlogic/ |
| D | meson-gxl-s905x-libretech-cc.dts | 46 emmc_pwrseq: emmc-pwrseq {
47 compatible = "mmc-pwrseq-emmc";
127 /* This is provided by LDOs on the eMMC daugther card */
268 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
269 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
270 "eMMC Clk", "eMMC Reset", "eMMC CMD",
271 "ALT BOOT MODE", "", "", "", "eMMC Data Strobe",
319 /* eMMC */
|
| D | meson-gxl-s905x-khadas-vim.dts | 180 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
181 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
182 "eMMC Clk", "eMMC Reset", "eMMC CMD",
183 "", "BOOT_MODE", "", "", "eMMC Data Strobe",
|
| D | meson-gxl-s805x-libretech-ac.dts | 53 emmc_pwrseq: emmc-pwrseq {
54 compatible = "mmc-pwrseq-emmc";
245 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
246 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
247 "eMMC Clk", "eMMC Reset", "eMMC CMD",
276 /* eMMC */
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/allwinner/ |
| D | sun7i-a20-olimex-som204-evb-emmc.dts | 3 * Device Tree Source for A20-SOM204-EVB-eMMC Board
13 model = "Olimex A20-SOM204-EVB-eMMC";
14 compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
17 compatible = "mmc-pwrseq-emmc";
29 emmc: emmc@0 { label
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| D | sun7i-a20-olimex-som-evb-emmc.dts | 3 * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board
14 model = "Olimex A20-Olimex-SOM-EVB-eMMC";
15 compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
18 compatible = "mmc-pwrseq-emmc";
30 emmc: emmc@0 { label
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/ |
| D | Makefile | 67 imx6dl-cubox-i-emmc-som-v15.dtb \
88 imx6dl-hummingboard-emmc-som-v15.dtb \
91 imx6dl-hummingboard2-emmc-som-v15.dtb \
159 imx6q-cubox-i-emmc-som-v15.dtb \
192 imx6q-hummingboard-emmc-som-v15.dtb \
195 imx6q-hummingboard2-emmc-som-v15.dtb \
212 imx6q-phytec-mira-rdk-emmc.dtb \
299 imx6ul-isiot-emmc.dtb \
311 imx6ul-phytec-segin-ff-rdk-emmc.dtb \
319 imx6ull-colibri-emmc-aster.dtb \
[all …]
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