Searched full:fpgas (Results 1 – 25 of 89) sorted by relevance
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9 Say Y here if you want support for configuring FPGAs from the53 Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.59 FPGA manager driver support for Xilinx Zynq FPGAs.78 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.98 processors and FPGAs or between FPGAs.232 FPGA manager driver support for Xilinx ZynqMP FPGAs.264 FPGA manager driver support for Microchip Polarfire FPGAs276 FPGA manager driver support for Lattice FPGAs programming over slave
9 Say Y here if you want support for configuring FPGAs from the53 Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.59 FPGA manager driver support for Xilinx Zynq FPGAs.78 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.98 processors and FPGAs or between FPGAs.214 FPGA manager driver support for Xilinx ZynqMP FPGAs.
27 FPGAs as well as CompactPCI attached MCB FPGAs are supported with
31 AXI bus interface used in Xilinx Virtex FPGAs and Soc's.38 core used in Xilinx Spartan and Virtex FPGAs
32 AXI bus interface used in Xilinx Virtex FPGAs and Soc's.40 core used in Xilinx Spartan and Virtex FPGAs
4 The FPGA subsystem supports reprogramming FPGAs dynamically under54 reprogramming FPGAs when device tree overlays are applied.
6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.15 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
18 Processor Interface (CAPI). CAPI allows accelerators in FPGAs to be
5 devices like FPGAs).
19 Processor Interface (CAPI). CAPI allows accelerators in FPGAs to be
25 LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
3 Lattice MachXO2 FPGAs support a method of loading the bitstream over
3 Altera FPGAs support a method of loading the bitstream over what is
4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range107 The Xilinx SystemACE device is used to program FPGAs from an FPGA
18 Altera family of FPGAs. In order to support Linux, Nios II needs to be configured
3 * in Altera's FPGAs.
30 on the Solarflare EF100 networking IP in Xilinx FPGAs.