| /kernel/linux/linux-5.10/drivers/iommu/ |
| D | tegra-gart.c | 10 #define dev_fmt(fmt) "gart: " fmt
58 #define FLUSH_GART_REGS(gart) readl_relaxed((gart)->regs + GART_CONFIG) argument
60 #define for_each_gart_pte(gart, iova) \ argument
61 for (iova = gart->iovmm_base; \
62 iova < gart->iovmm_end; \
65 static inline void gart_set_pte(struct gart_device *gart, in gart_set_pte() argument
68 writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR); in gart_set_pte()
69 writel_relaxed(pte, gart->regs + GART_ENTRY_DATA); in gart_set_pte()
72 static inline unsigned long gart_read_pte(struct gart_device *gart, in gart_read_pte() argument
77 writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR); in gart_read_pte()
[all …]
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| /kernel/linux/linux-6.6/drivers/iommu/ |
| D | tegra-gart.c | 10 #define dev_fmt(fmt) "gart: " fmt
58 #define FLUSH_GART_REGS(gart) readl_relaxed((gart)->regs + GART_CONFIG) argument
60 #define for_each_gart_pte(gart, iova) \ argument
61 for (iova = gart->iovmm_base; \
62 iova < gart->iovmm_end; \
65 static inline void gart_set_pte(struct gart_device *gart, in gart_set_pte() argument
68 writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR); in gart_set_pte()
69 writel_relaxed(pte, gart->regs + GART_ENTRY_DATA); in gart_set_pte()
72 static inline unsigned long gart_read_pte(struct gart_device *gart, in gart_read_pte() argument
77 writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR); in gart_read_pte()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| D | radeon_gart.c | 39 * GART
40 * The GART (Graphics Aperture Remapping Table) is an aperture
46 * Radeon GPUs support both an internal GART, as described above,
47 * and AGP. AGP works similarly, but the GART table is configured
52 * Both AGP and internal GART can be used at the same time, however
55 * This file handles the common internal GART management.
59 * Common GART table functions.
62 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
66 * Allocate system memory for GART page table
68 * gart table to be in system memory.
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| D | rs400.c | 44 /* Check gart size */ in rs400_gart_adjust_size()
55 DRM_ERROR("Unable to use IGP GART size %uM\n", in rs400_gart_adjust_size()
57 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); in rs400_gart_adjust_size()
58 DRM_ERROR("Forcing to 32M GART size\n"); in rs400_gart_adjust_size()
84 if (rdev->gart.ptr) { in rs400_gart_init()
85 WARN(1, "RS400 GART already initialized\n"); in rs400_gart_init()
88 /* Check gart size */ in rs400_gart_init()
101 /* Initialize common gart structure */ in rs400_gart_init()
106 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
118 /* Check gart size */ in rs400_gart_enable()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | radeon_gart.c | 39 * GART
40 * The GART (Graphics Aperture Remapping Table) is an aperture
46 * Radeon GPUs support both an internal GART, as described above,
47 * and AGP. AGP works similarly, but the GART table is configured
52 * Both AGP and internal GART can be used at the same time, however
55 * This file handles the common internal GART management.
59 * Common GART table functions.
62 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
66 * Allocate system memory for GART page table
68 * gart table to be in system memory.
[all …]
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| D | rs400.c | 45 /* Check gart size */ in rs400_gart_adjust_size()
56 DRM_ERROR("Unable to use IGP GART size %uM\n", in rs400_gart_adjust_size()
58 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); in rs400_gart_adjust_size()
59 DRM_ERROR("Forcing to 32M GART size\n"); in rs400_gart_adjust_size()
85 if (rdev->gart.ptr) { in rs400_gart_init()
86 WARN(1, "RS400 GART already initialized\n"); in rs400_gart_init()
89 /* Check gart size */ in rs400_gart_init()
102 /* Initialize common gart structure */ in rs400_gart_init()
107 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); in rs400_gart_init()
108 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_gart.c | 39 * GART
40 * The GART (Graphics Aperture Remapping Table) is an aperture
46 * Radeon GPUs support both an internal GART, as described above,
47 * and AGP. AGP works similarly, but the GART table is configured
52 * Both AGP and internal GART can be used at the same time, however
55 * This file handles the common internal GART management.
59 * Common GART table functions.
68 * This dummy page is used by the driver as a filler for gart entries
69 * when pages are taken out of the GART
105 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
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| D | gmc_v10_0.c | 188 * GART
201 /* Use register 17 for GART */ in gmc_v10_0_flush_vm_hub()
266 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
333 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); in gmc_v10_0_flush_gpu_tlb()
717 * vram and gart within the GPU's physical address space.
742 /* set the gart size */ in gmc_v10_0_mc_init()
766 if (adev->gart.bo) { in gmc_v10_0_gart_init()
767 WARN(1, "NAVI10 PCIE GART already initialized\n"); in gmc_v10_0_gart_init()
771 /* Initialize common gart structure */ in gmc_v10_0_gart_init()
776 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v10_0_gart_init()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_gart.c | 42 * GART
43 * The GART (Graphics Aperture Remapping Table) is an aperture
49 * Radeon GPUs support both an internal GART, as described above,
50 * and AGP. AGP works similarly, but the GART table is configured
55 * Both AGP and internal GART can be used at the same time, however
58 * This file handles the common internal GART management.
62 * Common GART table functions.
71 * This dummy page is used by the driver as a filler for gart entries
72 * when pages are taken out of the GART
108 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
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| D | amdgpu_gmc.c | 162 * The following is for PTE only. GART does not have PDEs. in amdgpu_gmc_set_pte_pde()
228 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture
233 * This function is only used if use GART for FB translation. In such
235 * and gart (aka system memory) access.
242 * address 0. So vram start at address 0 and gart is right after vram.
257 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", in amdgpu_gmc_sysvm_location()
262 * amdgpu_gmc_gart_location - try to find GART location
267 * Function will place try to place GART before or after VRAM.
268 * If GART size is bigger than space left then we ajust GART size.
279 * the GART base on a 4GB boundary as well. in amdgpu_gmc_gart_location()
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| /kernel/linux/linux-6.6/drivers/char/agp/ |
| D | i460-agp.c | 47 /* Control bits for Out-Of-GART coherency and Burst Write Combining */
69 /* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */
75 /* structure for tracking partial use of 4MB GART pages: */
87 * The 32GB aperture is only available with a 4M GART page size. Due to the
88 * dynamic GART page size, we can't figure out page_order or num_entries until
110 /* Determine the GART page size */ in i460_fetch_size()
117 "I/O (GART) page-size %luKB doesn't match expected " in i460_fetch_size()
128 /* Exit now if the IO drivers for the GART SRAMS are turned off */ in i460_fetch_size()
130 printk(KERN_ERR PFX "GART SRAMS disabled on 460GX chipset\n"); in i460_fetch_size()
137 printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n"); in i460_fetch_size()
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| D | Kconfig | 14 If you need more texture memory than you can get with the AGP GART
60 tristate "AMD Opteron/Athlon64 on-CPU GART support"
116 This option gives you AGP GART support for the Intel 460GX chipset
123 This option gives you AGP GART support for the HP ZX1 chipset
130 This option gives you AGP GART support for the HP Quicksilver
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| /kernel/linux/linux-5.10/drivers/char/agp/ |
| D | i460-agp.c | 47 /* Control bits for Out-Of-GART coherency and Burst Write Combining */
69 /* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */
75 /* structure for tracking partial use of 4MB GART pages: */
87 * The 32GB aperture is only available with a 4M GART page size. Due to the
88 * dynamic GART page size, we can't figure out page_order or num_entries until
110 /* Determine the GART page size */ in i460_fetch_size()
117 "I/O (GART) page-size %luKB doesn't match expected " in i460_fetch_size()
128 /* Exit now if the IO drivers for the GART SRAMS are turned off */ in i460_fetch_size()
130 printk(KERN_ERR PFX "GART SRAMS disabled on 460GX chipset\n"); in i460_fetch_size()
137 printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n"); in i460_fetch_size()
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| D | Kconfig | 14 If you need more texture memory than you can get with the AGP GART
60 tristate "AMD Opteron/Athlon64 on-CPU GART support"
116 This option gives you AGP GART support for the Intel 460GX chipset
123 This option gives you AGP GART support for the HP ZX1 chipset
130 This option gives you AGP GART support for the HP Quicksilver
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| /kernel/linux/linux-5.10/arch/x86/kernel/ |
| D | aperture_64.c | 29 #include <asm/gart.h>
39 * with the gart aperture that is used.
42 * ==> kexec (with kdump trigger path or gart still enabled)
43 * ==> kernel_small (gart area become e820_reserved)
44 * ==> kexec (with kdump trigger path or gart still enabled)
46 * So don't use 512M below as gart iommu, leave the space for kernel
173 /* old_order could be the value from NB gart setting */ in read_agp()
274 * With kexec/kdump, if the first kernel doesn't shut down the GART and the
275 * second kernel allocates a different GART region, there might be two
276 * overlapping GART regions present:
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| D | amd_gart_64.c | 5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
39 #include <asm/gart.h>
47 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
55 * of only flushing when an mapping is reused. With it true the GART is
81 /* GART can only remap to physical addresses < 1TB */
89 static bool need_flush; /* global flush state. set for each gart wrap */
259 * This driver will not always use a GART mapping, but might have in gart_unmap_page()
553 /* Flush the GART-TLB to remove stale entries */ in enable_gart_translations()
582 pr_info("PCI-DMA: Restoring GART aperture settings\n"); in gart_fixup_northbridges()
598 pr_info("PCI-DMA: Resuming GART IOMMU\n"); in gart_resume()
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| /kernel/linux/linux-6.6/arch/x86/kernel/ |
| D | aperture_64.c | 29 #include <asm/gart.h>
39 * the gart aperture that is used.
42 * ==> kexec (with kdump trigger path or gart still enabled)
43 * ==> kernel_small (gart area become e820_reserved)
44 * ==> kexec (with kdump trigger path or gart still enabled)
46 * So don't use 512M below as gart iommu, leave the space for kernel
183 /* old_order could be the value from NB gart setting */ in read_agp()
284 * With kexec/kdump, if the first kernel doesn't shut down the GART and the
285 * second kernel allocates a different GART region, there might be two
286 * overlapping GART regions present:
[all …]
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| D | amd_gart_64.c | 5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
39 #include <asm/gart.h>
45 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
53 * of only flushing when an mapping is reused. With it true the GART is
79 /* GART can only remap to physical addresses < 1TB */
87 static bool need_flush; /* global flush state. set for each gart wrap */
257 * This driver will not always use a GART mapping, but might have in gart_unmap_page()
551 /* Flush the GART-TLB to remove stale entries */ in enable_gart_translations()
580 pr_info("PCI-DMA: Restoring GART aperture settings\n"); in gart_fixup_northbridges()
596 pr_info("PCI-DMA: Resuming GART IOMMU\n"); in gart_resume()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra20-mc.txt | 4 - compatible : "nvidia,tegra20-mc-gart"
6 the controller's registers and the GART aperture respectively.
16 IOMMU specifier needed to encode an address. GART supports only a single
22 compatible = "nvidia,tegra20-mc-gart";
24 0x58000000 0x02000000>; /* GART aperture */
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra20-mc.yaml | 21 Tegra20 Memory Controller includes the GART (Graphics Address Relocation
27 const: nvidia,tegra20-mc-gart
32 - description: GART registers
68 compatible = "nvidia,tegra20-mc-gart";
70 <0x58000000 0x02000000>; /* GART aperture */
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| /kernel/linux/linux-6.6/arch/x86/include/asm/ |
| D | gart.h | 23 /* GART cache control register bits. */
27 /* K8 On-cpu GART registers */
66 * Don't enable translation but enable GART IO and CPU accesses. in gart_set_size_and_enable()
67 * Also, set DISTLBWALKPRB since GART tables memory is UC. in gart_set_size_and_enable()
84 /* Enable GART translation for this hammer. */ in enable_gart_translation()
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| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| D | gart.h | 23 /* GART cache control register bits. */
27 /* K8 On-cpu GART registers */
67 * Don't enable translation but enable GART IO and CPU accesses. in gart_set_size_and_enable()
68 * Also, set DISTLBWALKPRB since GART tables memory is UC. in gart_set_size_and_enable()
85 /* Enable GART translation for this hammer. */ in enable_gart_translation()
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| /kernel/linux/linux-5.10/include/soc/tegra/ |
| D | mc.h | 100 int tegra_gart_suspend(struct gart_device *gart);
101 int tegra_gart_resume(struct gart_device *gart);
109 static inline int tegra_gart_suspend(struct gart_device *gart) in tegra_gart_suspend() argument
114 static inline int tegra_gart_resume(struct gart_device *gart) in tegra_gart_resume() argument
168 struct gart_device *gart; member
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| /kernel/linux/linux-5.10/arch/powerpc/include/asm/ |
| D | uninorth.h | 53 * GART_BASE register appear to contain the physical address of the GART
55 * GART size in the low order bits (number of GART pages)
57 * The GART format itself is one 32bits word per physical memory page.
62 * Obviously, the GART is not cache coherent and so any change to it
63 * must be flushed to memory (or maybe just make the GART space non
66 * In order to invalidate the GART (which is probably necessary to inval
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| /kernel/linux/linux-6.6/arch/powerpc/include/asm/ |
| D | uninorth.h | 53 * GART_BASE register appear to contain the physical address of the GART
55 * GART size in the low order bits (number of GART pages)
57 * The GART format itself is one 32bits word per physical memory page.
62 * Obviously, the GART is not cache coherent and so any change to it
63 * must be flushed to memory (or maybe just make the GART space non
66 * In order to invalidate the GART (which is probably necessary to inval
|