| /kernel/linux/linux-6.6/arch/arm64/boot/dts/arm/ |
| D | rtsm_ve-aemv8a.dts | 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
99 gic: interrupt-controller@2c001000 { label
100 compatible = "arm,gic-400", "arm,cortex-a15-gic";
140 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | foundation-v8.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
137 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
138 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
139 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
140 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | fvp-base-revc.dts | 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
188 gic: interrupt-controller@2f000000 { label
189 compatible = "arm,gic-v3";
204 compatible = "arm,gic-v3-its";
237 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
238 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
239 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
240 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | rtsm_ve-aemv8a.dts | 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
97 gic: interrupt-controller@2c001000 { label
98 compatible = "arm,gic-400", "arm,cortex-a15-gic";
149 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
151 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
152 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
153 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
154 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | vexpress-v2f-1xv7-ca53x2.dts | 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
82 gic: interrupt-controller@2c001000 { label
83 compatible = "arm,gic-400";
161 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
162 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
163 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
164 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
165 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
166 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | fvp-base-revc.dts | 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
115 gic: interrupt-controller@2f000000 { label
116 compatible = "arm,gic-v3";
131 compatible = "arm,gic-v3-its";
164 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
165 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
166 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
167 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | foundation-v8.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
131 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
132 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
133 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
134 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
135 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
136 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
137 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
138 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-gic.c | 5 * Interrupt architecture for the GIC:
40 #include <linux/irqchip/arm-gic.h>
48 #include "irq-gic-common.h"
113 * The GIC mapping of CPU interfaces does not necessarily match
115 * by the GIC itself.
311 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); in gic_set_type()
320 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
339 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
340 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
355 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | vexpress-v2p-ca5s.dts | 19 interrupt-parent = <&gic>;
121 gic: interrupt-controller@2c001000 { label
122 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
224 interrupt-map = <0 0 0 &gic 0 0 4>,
225 <0 0 1 &gic 0 1 4>,
226 <0 0 2 &gic 0 2 4>,
227 <0 0 3 &gic 0 3 4>,
228 <0 0 4 &gic 0 4 4>,
229 <0 0 5 &gic 0 5 4>,
230 <0 0 6 &gic 0 6 4>,
[all …]
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| D | vexpress-v2p-ca15-tc1.dts | 19 interrupt-parent = <&gic>;
94 gic: interrupt-controller@2c001000 { label
95 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
253 interrupt-map = <0 0 0 &gic 0 0 4>,
254 <0 0 1 &gic 0 1 4>,
255 <0 0 2 &gic 0 2 4>,
256 <0 0 3 &gic 0 3 4>,
257 <0 0 4 &gic 0 4 4>,
258 <0 0 5 &gic 0 5 4>,
259 <0 0 6 &gic 0 6 4>,
[all …]
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| D | vexpress-v2p-ca9.dts | 19 interrupt-parent = <&gic>;
155 gic: interrupt-controller@1e001000 { label
156 compatible = "arm,cortex-a9-gic";
311 interrupt-map = <0 0 0 &gic 0 0 4>,
312 <0 0 1 &gic 0 1 4>,
313 <0 0 2 &gic 0 2 4>,
314 <0 0 3 &gic 0 3 4>,
315 <0 0 4 &gic 0 4 4>,
316 <0 0 5 &gic 0 5 4>,
317 <0 0 6 &gic 0 6 4>,
[all …]
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| D | bcm5301x.dtsi | 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-parent = <&gic>;
88 gic: interrupt-controller@21000 { label
89 compatible = "arm,cortex-a9-gic";
171 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
175 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
176 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
177 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
178 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | vexpress-v2p-ca15_a7.dts | 19 interrupt-parent = <&gic>;
149 gic: interrupt-controller@2c001000 { label
150 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
625 interrupt-map = <0 0 0 &gic 0 0 4>,
626 <0 0 1 &gic 0 1 4>,
627 <0 0 2 &gic 0 2 4>,
628 <0 0 3 &gic 0 3 4>,
629 <0 0 4 &gic 0 4 4>,
630 <0 0 5 &gic 0 5 4>,
631 <0 0 6 &gic 0 6 4>,
[all …]
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| D | bcm53573.dtsi | 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-gic.c | 5 * Interrupt architecture for the GIC:
42 #include <linux/irqchip/arm-gic.h>
50 #include "irq-gic-common.h"
114 * The GIC mapping of CPU interfaces does not necessarily match
116 * by the GIC itself.
312 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); in gic_set_type()
321 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
340 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
341 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
356 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
[all …]
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| D | mti,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
[all …]
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| D | renesas,rza1-irqc.yaml | 14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
[all …]
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| D | mti,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
[all …]
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| D | renesas,rza1-irqc.yaml | 14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/ |
| D | bcm-ns.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
68 gic: interrupt-controller@21000 { label
69 compatible = "arm,cortex-a9-gic";
99 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
102 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
103 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
104 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
105 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
106 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | bcm53573.dtsi | 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/arm/ |
| D | vexpress-v2m-rs1.dtsi | 20 #include <dt-bindings/interrupt-controller/arm-gic.h>
111 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
119 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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| D | vexpress-v2m.dtsi | 20 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
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