Searched full:gics (Results 1 – 11 of 11) sorted by relevance
18 Secondary GICs are cascaded into the upward interrupt controller and do not105 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
18 Secondary GICs are cascaded into the upward interrupt controller and do not113 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
144 * chips and call this to register their GICs.
47 * "performance interrupt". Luckily, on compliant GICs the polarity is in arm_pmu_acpi_register_irq()
48 * "performance interrupt". Luckily, on compliant GICs the polarity is in arm_pmu_acpi_register_irq()
629 MADT for GICs are expected to be in synchronization. The _UID of the Device698 - Section 9.17: I/O APIC devices; all GICs must be enumerable via MADT
700 MADT for GICs are expected to be in synchronization. The _UID of the Device769 - Section 9.17: I/O APIC devices; all GICs must be enumerable via MADT
580 * If we get one of these oddball non-GICs, taint the kernel, in kvm_vgic_hyp_init()
504 * because any nested/secondary GICs do not directly interface in gic_cpu_init()1218 * For primary GICs, skip over SGIs. in gic_init_bases()
499 * because any nested/secondary GICs do not directly interface in gic_cpu_init()