| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | qcom,mmcc.yaml | 113 - description: MMSS GPLL0 voted clock
114 - description: GPLL0 voted clock
141 - description: MMSS GPLL0 voted clock
142 - description: GPLL0 voted clock
180 - description: MMSS GPLL0 voted clock
181 - description: GPLL0 clock
182 - description: GPLL0 voted clock
197 - const: gpll0
244 - const: gpll0
274 - const: gpll0
[all …]
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| D | qcom,msm8998-gpucc.yaml | 25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
30 - const: gpll0
66 clock-names = "xo", "gpll0";
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| D | qcom,sm6115-gpucc.yaml | 26 - description: GPLL0 main branch source
27 - description: GPLL0 main div source
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| D | qcom,sm8450-gpucc.yaml | 30 - description: GPLL0 main branch source
31 - description: GPLL0 div branch source
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| D | qcom,gpucc-sdm660.yaml | 27 - description: GPLL0 main gpu branch
28 - description: GPLL0 divider gpu branch
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| D | qcom,sm6375-gpucc.yaml | 26 - description: GPLL0 main branch source
27 - description: GPLL0 div branch source
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| D | qcom,qcm2290-dispcc.yaml | 26 - description: GPLL0 source from GCC
27 - description: GPLL0 div source from GCC
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| D | qcom,sdm845-dispcc.yaml | 28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
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| D | qcom,gpucc.yaml | 44 - description: GPLL0 main branch source
45 - description: GPLL0 div branch source
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | qcom,msm8998-gpucc.yaml | 25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
30 - const: gpll0
66 clock-names = "xo", "gpll0";
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| D | qcom,gpucc.yaml | 33 - description: GPLL0 main branch source
34 - description: GPLL0 div branch source
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| D | qcom,sdm845-dispcc.yaml | 28 - description: GPLL0 source from GCC
29 - description: GPLL0 div source from GCC
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interconnect/ |
| D | qcom,osm-l3.yaml | 53 #define GPLL0 165
60 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interconnect/ |
| D | qcom,osm-l3.yaml | 66 #define GPLL0 165
73 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | gcc-sc7180.c | 36 static struct clk_alpha_pll gpll0 = { variable
43 .name = "gpll0",
69 .hw = &gpll0.clkr.hw,
82 .hw = &gpll0.clkr.hw,
170 { .hw = &gpll0.clkr.hw },
177 { .hw = &gpll0.clkr.hw },
192 { .hw = &gpll0.clkr.hw },
209 { .hw = &gpll0.clkr.hw },
224 { .hw = &gpll0.clkr.hw },
238 { .hw = &gpll0.clkr.hw },
[all …]
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| D | mmcc-msm8998.c | 56 .fw_name = "gpll0",
57 .name = "gpll0"
375 { .fw_name = "gpll0", .name = "gpll0" },
391 { .fw_name = "gpll0", .name = "gpll0" },
409 { .fw_name = "gpll0", .name = "gpll0" },
427 { .fw_name = "gpll0", .name = "gpll0" },
447 { .fw_name = "gpll0", .name = "gpll0" },
467 { .fw_name = "gpll0", .name = "gpll0" },
487 { .fw_name = "gpll0", .name = "gpll0" },
509 { .fw_name = "gpll0", .name = "gpll0" },
|
| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | gcc-sc7180.c | 35 static struct clk_alpha_pll gpll0 = { variable
42 .name = "gpll0",
68 &gpll0.clkr.hw,
81 &gpll0.clkr.hw,
168 { .hw = &gpll0.clkr.hw },
174 { .hw = &gpll0.clkr.hw },
187 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
215 { .hw = &gpll0.clkr.hw },
227 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-sm7150.c | 41 static struct clk_alpha_pll gpll0 = { variable
48 .name = "gpll0",
76 &gpll0.clkr.hw,
89 &gpll0.clkr.hw,
138 { .hw = &gpll0.clkr.hw },
143 { .hw = &gpll0.clkr.hw },
156 { .hw = &gpll0.clkr.hw },
168 { .hw = &gpll0.clkr.hw },
173 { .hw = &gpll0.clkr.hw },
203 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-qcm2290.c | 57 static struct clk_alpha_pll gpll0 = { variable
64 .name = "gpll0",
88 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
416 { .hw = &gpll0.clkr.hw },
429 { .hw = &gpll0.clkr.hw },
443 { .hw = &gpll0.clkr.hw },
459 { .hw = &gpll0.clkr.hw },
477 { .hw = &gpll0.clkr.hw },
494 { .hw = &gpll0.clkr.hw },
512 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-sm6115.c | 57 static struct clk_alpha_pll gpll0 = { variable
66 .name = "gpll0",
90 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
110 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
475 { .hw = &gpll0.clkr.hw },
488 { .hw = &gpll0.clkr.hw },
502 { .hw = &gpll0.clkr.hw },
517 { .hw = &gpll0.clkr.hw },
532 { .hw = &gpll0.clkr.hw },
548 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-sm6375.c | 61 static struct clk_alpha_pll gpll0 = { variable
68 .name = "gpll0",
93 &gpll0.clkr.hw,
115 &gpll0.clkr.hw,
447 { .hw = &gpll0.clkr.hw },
460 { .hw = &gpll0.clkr.hw },
474 { .hw = &gpll0.clkr.hw },
481 { .hw = &gpll0.clkr.hw },
497 { .hw = &gpll0.clkr.hw },
515 { .hw = &gpll0.clkr.hw },
[all …]
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| D | gcc-mdm9607.c | 54 static struct clk_alpha_pll_postdiv gpll0 = { variable
59 .name = "gpll0",
73 { .hw = &gpll0.clkr.hw },
114 { .hw = &gpll0.clkr.hw },
157 { .hw = &gpll0.clkr.hw },
170 { .hw = &gpll0.clkr.hw },
232 { .hw = &gpll0.clkr.hw },
1477 [GPLL0] = &gpll0.clkr,
1604 /* Vote for GPLL0 to turn on. Needed by acpuclock. */ in gcc_mdm9607_probe()
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| D | gcc-sdx55.c | 36 static struct clk_alpha_pll gpll0 = { variable
45 .name = "gpll0",
73 &gpll0.clkr.hw,
143 { .hw = &gpll0.clkr.hw },
149 { .hw = &gpll0.clkr.hw },
163 { .hw = &gpll0.clkr.hw },
178 { .hw = &gpll0.clkr.hw },
202 { .hw = &gpll0.clkr.hw },
1556 [GPLL0] = &gpll0.clkr,
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,msm8996-mss-pil.yaml | 220 - description: GCC MSS GPLL0 clock
258 - description: GCC MSS GPLL0 clock
295 - description: GCC MSS GPLL0 clock
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.txt | 16 Definition: clock handle for XO clock and GPLL0 clock.
167 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|