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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dmvebu-gated-clock.txt7 corresponding clock gating control bit in HW to ease manual clock
177 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 "marvell,dove-gating-clock" - for Dove SoC clock gating
184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
[all …]
Dzx296718-clk.txt10 zx296718 top clock selection, divider and gating
14 zx296718 device level clock selection and gating
17 zx296718 audio clock selection, divider and gating
Dzx296702-clk.txt10 zx296702 top clock selection, divider and gating
14 zx296702 device level clock selection and gating
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dmvebu-gated-clock.txt7 corresponding clock gating control bit in HW to ease manual clock
177 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 "marvell,dove-gating-clock" - for Dove SoC clock gating
184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
[all …]
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dclk-branch.h12 * struct clk_branch - gating clock with status bit and dynamic hardware gating
14 * @hwcg_reg: dynamic hardware clock gating register
15 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
/kernel/linux/linux-5.10/drivers/staging/gasket/
Dapex.h12 /* Clock Gating ioctl. */
17 /* If set, enter clock gating state, regardless of custom block's
26 /* Enable/Disable clock gating. */
/kernel/linux/linux-5.10/sound/soc/intel/catpt/
Ddsp.c169 /* wait for SRAM power gating to propagate */ in catpt_dsp_set_srampge()
207 /* disable core clock gating */ in catpt_dsp_update_srampge()
212 /* enable core clock gating */ in catpt_dsp_update_srampge()
366 /* DRAM power gating all */ in lpt_dsp_power_down()
381 /* SRAM power gating none */ in lpt_dsp_power_up()
407 /* disable core clock gating */ in wpt_dsp_power_down()
420 /* switch clock gating */ in wpt_dsp_power_down()
428 /* SRAM power gating all */ in wpt_dsp_power_down()
440 /* enable core clock gating */ in wpt_dsp_power_down()
452 /* disable core clock gating */ in wpt_dsp_power_up()
[all …]
/kernel/linux/linux-6.6/drivers/clk/qcom/
Dclk-branch.h13 * struct clk_branch - gating clock with status bit and dynamic hardware gating
15 * @hwcg_reg: dynamic hardware clock gating register
16 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
/kernel/linux/linux-6.6/sound/soc/intel/catpt/
Ddsp.c169 /* wait for SRAM power gating to propagate */ in catpt_dsp_set_srampge()
207 /* disable core clock gating */ in catpt_dsp_update_srampge()
212 /* enable core clock gating */ in catpt_dsp_update_srampge()
361 /* disable core clock gating */ in catpt_dsp_power_down()
374 /* switch clock gating */ in catpt_dsp_power_down()
382 /* SRAM power gating all */ in catpt_dsp_power_down()
394 /* enable core clock gating */ in catpt_dsp_power_down()
406 /* disable core clock gating */ in catpt_dsp_power_up()
409 /* switch clock gating */ in catpt_dsp_power_up()
416 /* SRAM power gating none */ in catpt_dsp_power_up()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_sseu.c160 /* TGL only supports slice-level power gating */ in gen12_sseu_info_init()
186 /* ICL has no power gating restrictions. */ in gen11_sseu_info_init()
263 /* No restrictions on Power Gating */ in gen10_sseu_info_init()
315 * CHV supports subslice power gating on devices with more than in cherryview_sseu_info_init()
316 * one subslice, and supports EU power gating on devices with in cherryview_sseu_info_init()
401 * SKL+ supports slice power gating on devices with more than in gen9_sseu_info_init()
402 * one slice, and supports EU power gating on devices with in gen9_sseu_info_init()
404 * power gating on devices with more than one subslice, and in gen9_sseu_info_init()
405 * supports EU power gating on devices with more than one EU in gen9_sseu_info_init()
508 * BDW supports slice power gating on devices with more than in bdw_sseu_info_init()
[all …]
/kernel/linux/linux-6.6/drivers/soc/tegra/
Dflowctrl.c84 /* pwr gating on wfe */ in flowctrl_cpu_suspend_enter()
99 * power-gating (like memory running off PLLP), in flowctrl_cpu_suspend_enter()
103 * while wfe for the power-gating, just like it in flowctrl_cpu_suspend_enter()
108 /* pwr gating on wfi */ in flowctrl_cpu_suspend_enter()
115 reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ in flowctrl_cpu_suspend_enter()
/kernel/linux/linux-5.10/drivers/soc/tegra/
Dflowctrl.c84 /* pwr gating on wfe */ in flowctrl_cpu_suspend_enter()
99 * power-gating (like memory running off PLLP), in flowctrl_cpu_suspend_enter()
103 * while wfe for the power-gating, just like it in flowctrl_cpu_suspend_enter()
108 /* pwr gating on wfi */ in flowctrl_cpu_suspend_enter()
115 reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ in flowctrl_cpu_suspend_enter()
/kernel/linux/linux-5.10/drivers/clk/bcm/
Dclk-kona.h106 * Gating control and status is managed by a 32-bit gate register.
108 * There are several types of gating available:
111 * - hardware-only gating (auto-gating)
116 * - software-only gating
117 * Auto-gating is not available for this type of clock.
121 * To ensure a change to the gating status is complete, the
124 * - selectable hardware or software gating
125 * Gating for this type of clock can be configured to be either
133 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
/kernel/linux/linux-6.6/drivers/clk/bcm/
Dclk-kona.h98 * Gating control and status is managed by a 32-bit gate register.
100 * There are several types of gating available:
103 * - hardware-only gating (auto-gating)
108 * - software-only gating
109 * Auto-gating is not available for this type of clock.
113 * To ensure a change to the gating status is complete, the
116 * - selectable hardware or software gating
117 * Gating for this type of clock can be configured to be either
125 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
/kernel/linux/linux-5.10/arch/arm/mach-ux500/
Dpm_domains.c21 * Handle the gating of the PM domain regulator here. in pd_power_off()
25 * callbacks, to be able to enable PM domain gating/ungating. in pd_power_off()
37 * callbacks, to be able to enable PM domain gating/ungating. in pd_power_on()
/kernel/linux/linux-6.6/drivers/pmdomain/st/
Dste-ux500-pm-domain.c23 * Handle the gating of the PM domain regulator here. in pd_power_off()
27 * callbacks, to be able to enable PM domain gating/ungating. in pd_power_off()
39 * callbacks, to be able to enable PM domain gating/ungating. in pd_power_on()
/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
Dpsb_device.c89 u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL); in psb_init_pm() local
90 gating &= ~3; /* Disable 2D clock gating */ in psb_init_pm()
91 gating |= 1; in psb_init_pm()
92 PSB_WSGX32(gating, PSB_CR_CLKGATECTL); in psb_init_pm()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
Dintel_sseu.c293 /* TGL only supports slice-level power gating */ in gen12_sseu_info_init()
325 /* ICL has no power gating restrictions. */ in gen11_sseu_info_init()
374 * CHV supports subslice power gating on devices with more than in cherryview_sseu_info_init()
375 * one subslice, and supports EU power gating on devices with in cherryview_sseu_info_init()
459 * SKL+ supports slice power gating on devices with more than in gen9_sseu_info_init()
460 * one slice, and supports EU power gating on devices with in gen9_sseu_info_init()
462 * power gating on devices with more than one subslice, and in gen9_sseu_info_init()
463 * supports EU power gating on devices with more than one EU in gen9_sseu_info_init()
566 * BDW supports slice power gating on devices with more than in bdw_sseu_info_init()
722 * Starting in Gen9, render power gating can leave in intel_sseu_make_rpcs()
[all …]
/kernel/linux/linux-6.6/drivers/platform/x86/intel/pmc/
DKconfig20 - PCH IP Power Gating status
22 - MPHY/PLL gating status (Sunrisepoint PCH only)
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c535 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating
540 * Disable static power gating for VCN block
600 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating
605 * Enable static power gating for VCN block
655 * vcn_v4_0_disable_clock_gating - disable VCN clock gating
660 * Disable clock gating for VCN block
766 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
773 * Disable clock gating for VCN block with dpg mode
783 /* enable sw clock gating control */ in vcn_v4_0_disable_clock_gating_dpg_mode()
809 /* turn off clock gating */ in vcn_v4_0_disable_clock_gating_dpg_mode()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/
Dhardwaremanager.h95 …PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or…
96 …PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Sh…
98 PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */
148 …PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from…
149 …PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, suppor…
150 …PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for …
151 …PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for…
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/inc/
Dhardwaremanager.h94 …PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or…
95 …PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Sh…
97 PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */
147 …PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from…
148 …PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, suppor…
149 …PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for …
150 …PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for…
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
Dpsb_device.c154 u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL); in psb_init_pm() local
155 gating &= ~3; /* Disable 2D clock gating */ in psb_init_pm()
156 gating |= 1; in psb_init_pm()
157 PSB_WSGX32(gating, PSB_CR_CLKGATECTL); in psb_init_pm()
/kernel/linux/linux-6.6/drivers/gpu/drm/meson/
Dmeson_dw_mipi_dsi.h36 * 0=Default, use auto-clock gating to save power;
37 * 1=use free-run clock, disable auto-clock gating, for debug mode.
39 * have auto-clock gating. 1=Enable pixclk. Default 0.
41 * have auto-clock gating. 1=Enable sysclk. Default 0.
/kernel/linux/linux-5.10/sound/pci/hda/
Dhda_jack.c196 /* A gating jack indicates the jack is invalid if gating is unplugged */ in jack_detect_update()
365 * snd_hda_jack_set_gating_jack - Set gating jack.
368 * @gating_nid: gating pin NID
370 * Indicates the gated jack is only valid when the gating jack is plugged.
376 struct hda_jack_tbl *gating = in snd_hda_jack_set_gating_jack() local
381 if (!gated || !gating) in snd_hda_jack_set_gating_jack()
385 gating->gated_jack = gated_nid; in snd_hda_jack_set_gating_jack()
407 * to make sure that all gating jacks properly have been set in snd_hda_jack_report_sync()

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