| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/riscv/ |
| D | riscv-sbi-firmware.json | 39 "PublicDescription": "Sent IPI to other HART event",
42 "BriefDescription": "Sent IPI to other HART event"
45 "PublicDescription": "Received IPI from other HART event",
48 "BriefDescription": "Received IPI from other HART event"
51 "PublicDescription": "Sent FENCE.I request to other HART event",
54 "BriefDescription": "Sent FENCE.I request to other HART event"
57 "PublicDescription": "Received FENCE.I request from other HART event",
60 "BriefDescription": "Received FENCE.I request from other HART event"
63 "PublicDescription": "Sent SFENCE.VMA request to other HART event",
66 "BriefDescription": "Sent SFENCE.VMA request to other HART event"
[all …]
|
| /kernel/linux/linux-6.6/arch/riscv/kernel/ |
| D | cpu.c | 26 * Returns the hart ID of the given device tree node, or -ENODEV if the node
27 * isn't an enabled and valid RISC-V hart node.
29 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
33 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
34 if (*hart == ~0UL) { in riscv_of_processor_hartid()
35 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
39 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
49 int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_early_of_processor_hartid() argument
58 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_early_of_processor_hartid()
59 if (*hart == ~0UL) { in riscv_early_of_processor_hartid()
[all …]
|
| D | smpboot.c | 84 unsigned long hart; in acpi_parse_rintc() local
101 hart = processor->hart_id; in acpi_parse_rintc()
102 if (hart == INVALID_HARTID) { in acpi_parse_rintc()
107 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc()
119 cpuid_to_hartid_map(cpu_count) = hart; in acpi_parse_rintc()
148 unsigned long hart; in of_parse_and_init_cpus() local
156 rc = riscv_early_of_processor_hartid(dn, &hart); in of_parse_and_init_cpus()
160 if (hart == cpuid_to_hartid_map(0)) { in of_parse_and_init_cpus()
168 cpuid, hart); in of_parse_and_init_cpus()
172 cpuid_to_hartid_map(cpuid) = hart; in of_parse_and_init_cpus()
|
| D | machine_kexec.c | 133 * No more interrupts on this hart in machine_shutdown()
195 * suspended and this hart will be the new boot hart.
219 pr_notice("Will call new kernel at %08lx from hart id %lx\n", in machine_kexec()
223 /* Make sure the relocation code is visible to the hart */ in machine_kexec()
|
| /kernel/linux/linux-5.10/arch/riscv/kernel/ |
| D | cpu.c | 12 * Returns the hart ID of the given device tree node, or -ENODEV if the node
13 * isn't an enabled and valid RISC-V hart node.
18 u32 hart; in riscv_of_processor_hartid() local
25 if (of_property_read_u32(node, "reg", &hart)) { in riscv_of_processor_hartid()
26 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
31 pr_info("CPU with hartid=%d is not available\n", hart); in riscv_of_processor_hartid()
36 pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); in riscv_of_processor_hartid()
40 pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa); in riscv_of_processor_hartid()
44 return hart; in riscv_of_processor_hartid()
48 * Find hart ID of the CPU DT node under which given DT node falls.
[all …]
|
| D | smpboot.c | 70 int hart; in setup_smp() local
77 hart = riscv_of_processor_hartid(dn); in setup_smp()
78 if (hart < 0) in setup_smp()
81 if (hart == cpuid_to_hartid_map(0)) { in setup_smp()
88 cpuid, hart); in setup_smp()
92 cpuid_to_hartid_map(cpuid) = hart; in setup_smp()
|
| D | head.S | 181 /* We lack SMP support or have too many harts, so park this hart */
241 /* Pick one hart to run the main boot sequence */
257 /* Save hart ID and DTB physical address */
299 * This hart didn't win the lottery, so we wait for the winning hart to
|
| /kernel/linux/linux-5.10/arch/riscv/mm/ |
| D | cacheflush.c | 33 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
36 * execution resumes on each hart.
45 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
48 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
62 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
63 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
65 * messages are sent we still need to order this hart's writes in flush_icache_mm()
|
| D | context.c | 17 * behavior in a common case (a bunch of single-hart processes on a many-hart
20 * cache flush to be performed before execution resumes on each hart. This
22 * refers to the current hart.
33 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/addac/ |
| D | adi,ad74115.yaml | 70 10 - Current output with HART
71 11 - Current input, externally-powered, with HART
72 12 - Current input, loop-powered, with HART
188 adi,dac-hart-slew:
190 description: Whether to use a HART-compatible slew rate.
268 3 - Control HART CD
269 4 - Monitor HART CD
270 5 - Monitor HART EOM status
282 3 - Control HART RXD
283 4 - Monitor HART RXD
[all …]
|
| /kernel/linux/linux-6.6/arch/riscv/mm/ |
| D | cacheflush.c | 34 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
37 * execution resumes on each hart.
46 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
49 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
63 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
64 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
66 * messages are sent we still need to order this hart's writes in flush_icache_mm()
|
| D | context.c | 242 * we polluted the TLB of current HART so let's do TLB flushed in asids_init()
291 * behavior in a common case (a bunch of single-hart processes on a many-hart
294 * cache flush to be performed before execution resumes on each hart. This
296 * refers to the current hart.
308 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
|
| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-riscv-intc.c | 38 * on the local hart, these functions can only be called on the hart that
81 * for the per-HART local interrupts and child irqchip drivers in riscv_intc_irq_eoi()
83 * chained handlers for the per-HART local interrupts. in riscv_intc_irq_eoi()
87 * will do unnecessary mask/unmask of per-HART local interrupts in riscv_intc_irq_eoi()
197 pr_warn("unable to find hart id for %pOF\n", node); in riscv_intc_init()
202 * The DT will have one INTC DT node under each CPU (or HART) in riscv_intc_init()
205 * for the INTC DT node belonging to boot CPU (or boot HART). in riscv_intc_init()
242 * The ACPI MADT will have one INTC for each CPU (or HART) in riscv_intc_acpi_init()
245 * for the INTC belonging to the boot CPU (or boot HART). in riscv_intc_acpi_init()
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
|
| D | sifive,plic-1.0.0.yaml | 14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
17 A hart context is a privilege mode in a hardware execution thread. For example,
19 privilege modes per hart; machine mode and supervisor mode.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
|
| D | sifive,plic-1.0.0.yaml | 14 hart contexts in the system, via the external interrupt source in each hart.
16 A hart context is a privilege mode in a hardware execution thread. For example,
18 privilege modes per hart; machine mode and supervisor mode.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 17 hart: A hardware execution context, which contains all the state
39 Identifies that the hart uses the RISC-V instruction set
40 and identifies the type of the hart.
45 hart. These values originate from the RISC-V Privileged
57 supported by the hart. These are documented in the RISC-V
145 // Example 2: Spike ISA Simulator with 1 Hart
|
| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-riscv-intc.c | 48 * on the local hart, these functions can only be called on the hart that
102 pr_warn("unable to find hart id for %pOF\n", node); in riscv_intc_init()
107 * The DT will have one INTC DT node under each CPU (or HART) in riscv_intc_init()
110 * for the INTC DT node belonging to boot CPU (or boot HART). in riscv_intc_init()
|
| /kernel/linux/linux-5.10/arch/csky/abiv2/ |
| D | cacheflush.c | 40 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
64 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range()
68 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
|
| /kernel/linux/linux-6.6/arch/riscv/include/asm/ |
| D | cpu_ops_sbi.h | 16 * struct sbi_hart_boot_data - Hart specific boot used during booting and
18 * @task_ptr: A pointer to the hart specific tp
19 * @stack_ptr: A pointer to the hart specific sp
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 18 hart: A hardware execution context, which contains all the state
59 Identifies that the hart uses the RISC-V instruction set
60 and identifies the type of the hart.
65 hart. These values originate from the RISC-V Privileged
117 by this hart (see ./idle-states.yaml).
193 // Example 2: Spike ISA Simulator with 1 Hart
|
| /kernel/linux/linux-6.6/arch/csky/abiv2/ |
| D | cacheflush.c | 47 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
71 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range()
75 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
|
| /kernel/linux/linux-6.6/tools/testing/selftests/futex/ |
| D | run.sh | 13 # Darren Hart <dvhart@linux.intel.com>
16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
|
| /kernel/linux/linux-5.10/tools/testing/selftests/futex/ |
| D | run.sh | 13 # Darren Hart <dvhart@linux.intel.com>
16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
|