Searched full:harts (Results 1 – 25 of 27) sorted by relevance
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| /kernel/linux/linux-5.10/arch/riscv/kernel/ |
| D | sbi.c | 97 * sbi_shutdown() - Remove all the harts from executing supervisor code.
363 * @hart_mask: A cpu mask containing all the target harts.
374 * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
375 * @hart_mask: A cpu mask containing all the target harts.
388 * harts for the specified virtual address range.
389 * @hart_mask: A cpu mask containing all the target harts.
406 * remote harts for a virtual address range belonging to a specific ASID.
408 * @hart_mask: A cpu mask containing all the target harts.
427 * harts for the specified guest physical address range.
428 * @hart_mask: A cpu mask containing all the target harts.
[all …]
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| D | head.S | 181 /* We lack SMP support or have too many harts, so park this hart */
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| /kernel/linux/linux-6.6/arch/riscv/kernel/ |
| D | sbi.c | 124 * sbi_shutdown() - Remove all the harts from executing supervisor code.
368 * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
369 * @cpu_mask: A cpu mask containing all the target harts.
382 * remote harts for a virtual address range belonging to a specific ASID or not.
384 * @cpu_mask: A cpu mask containing all the target harts.
408 * harts for the specified guest physical address range.
409 * @cpu_mask: A cpu mask containing all the target harts.
426 * remote harts for a guest physical address range belonging to a specific VMID.
428 * @cpu_mask: A cpu mask containing all the target harts.
447 * harts for the current guest virtual address range.
[all …]
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| D | machine_kexec.c | 128 * harts and possibly devices etc) for a kexec reboot.
194 * executed. We assume at this point that all other harts are
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| D | sys_riscv.c | 202 * extensions are supported on all harts, and only supports the in hwprobe_one_pair()
318 * all harts, then assume all CPUs are the same, and allow the vDSO to in init_hwprobe_vdso_data()
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| D | head.S | 191 /* We lack SMP support or have too many harts, so park this hart */
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| /kernel/linux/linux-6.6/arch/riscv/mm/ |
| D | cacheflush.c | 32 * informs the remote harts they need to flush their local instruction caches.
35 * IPIs for harts that are not currently executing a MM context and instead
55 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm()
117 pr_warn("%s mismatched between harts %lu and %lu\n", in cbo_get_block_size()
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| D | context.c | 212 * The mm_cpumask indicates which harts' TLBs contain the virtual in set_mm()
289 * shoot downs, so instead we send an IPI that informs the remote harts they
292 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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| /kernel/linux/linux-5.10/arch/riscv/mm/ |
| D | cacheflush.c | 31 * informs the remote harts they need to flush their local instruction caches.
34 * IPIs for harts that are not currently executing a MM context and instead
54 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm()
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| D | context.c | 15 * shoot downs, so instead we send an IPI that informs the remote harts they
18 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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| /kernel/linux/linux-6.6/Documentation/riscv/ |
| D | boot.rst | 68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart
69 wins a lottery and executes the early boot code while the other harts are
73 initialization phase and then will start all other harts using the SBI HSM
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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| /kernel/linux/linux-5.10/arch/csky/abiv2/ |
| D | cacheflush.c | 74 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm_range()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| D | sifive,plic-1.0.0.yaml | 18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| D | sifive,plic-1.0.0.yaml | 17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| /kernel/linux/linux-6.6/arch/csky/abiv2/ |
| D | cacheflush.c | 81 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm_range()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 23 having four harts.
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-riscv.c | 41 * It is guaranteed that all the timers across all the harts are synchronized
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| /kernel/linux/linux-6.6/drivers/clocksource/ |
| D | timer-riscv.c | 62 * It is guaranteed that all the timers across all the harts are synchronized
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 24 having four harts.
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| /kernel/linux/linux-6.6/drivers/perf/ |
| D | riscv_pmu_sbi.c | 58 * RISC-V doesn't have heterogeneous harts yet. This need to be part of
59 * per_cpu in case of harts with different pmu counters
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| /kernel/linux/linux-6.6/arch/riscv/kvm/ |
| D | aia.c | 585 * run on other HARTs in kvm_riscv_aia_disable()
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