Searched full:hs400 (Results 1 – 25 of 217) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | mtk-sd.txt | 38 - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
39 - hs400-ds-delay: HS400 DS delay setting
43 - mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
46 - mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
47 If present,HS400 command responses are sampled on rising edges.
48 If not present,HS400 command responses are sampled on falling edges.
71 hs400-ds-delay = <0x14015>;
73 mediatek,hs400-cmd-int-delay = <14>;
74 mediatek,hs400-cmd-resp-sel-rising;
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| D | nvidia,tegra20-sdhci.txt | 79 - nvidia,pad-autocal-pull-up-offset-hs400,
80 nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
81 calibration offsets for HS400 mode.
86 - nvidia,dqs-trim : Specify DQS trim value for HS400 timing
94 - The SDR104 and HS400 timing specific values are used in
104 HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
105 HS400.
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| D | exynos-dw-mshc.txt | 39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
40 shift value for hs400 mode operation.
55 * samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
89 samsung,dw-mshc-hs400-timing = <0 2>;
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| D | cdns,sdhci.yaml | 93 HS200, HS400 and HS400_ES.
100 Value of the delay introduced on the sdclk output for HS200, HS400 and
109 HS400 / HS400_ES speed modes.
132 mmc-hs400-1_8v;
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| D | sdhci-sprd.txt | 40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
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| D | mmc-controller.yaml | 206 mmc-hs400-1_2v:
209 eMMC HS400 mode (1.2V I/O) is supported.
211 mmc-hs400-1_8v:
214 eMMC HS400 mode (1.8V I/O) is supported.
216 mmc-hs400-enhanced-strobe:
219 eMMC HS400 enhanced strobe mode is supported
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| D | sdhci-am654.yaml | 111 ti,otap-del-sel-hs400:
112 description: Output tap delay for eMMC HS400 timing
174 description: strobe select delay for HS400 speed mode.
213 ti,otap-del-sel-hs400 = <0x0>;
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| D | brcm,sdhci-brcmstb.txt | 39 mmc-hs400-1_8v;
40 mmc-hs400-enhanced-strobe;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/ |
| D | mtk-sd.yaml | 94 hs400-ds-delay:
97 HS400 DS delay setting.
110 mediatek,hs400-cmd-int-delay:
113 HS400 command internal delay setting.
119 mediatek,hs400-cmd-resp-sel-rising:
122 HS400 command response sample selection.
123 If present, HS400 command responses are sampled on rising edges.
124 If not present, HS400 command responses are sampled on falling edges.
126 mediatek,hs400-ds-dly3:
134 value with corner IC and it is valid only for HS400 mode.
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| D | nvidia,tegra20-sdhci.yaml | 100 The DQS trim values are only used on controllers which support HS400
101 timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
109 description: Specify DQS trim value for HS400 timing.
136 nvidia,pad-autocal-pull-down-offset-hs400:
137 description: Specify drive strength calibration offsets for HS400 mode.
158 and HS400 timing specific values are used in corresponding modes if
171 nvidia,pad-autocal-pull-up-offset-hs400:
172 description: Specify drive strength calibration offsets for HS400 mode.
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| D | samsung,exynos-dw-mshc.yaml | 63 See also samsung,dw-mshc-hs400-timing property.
65 samsung,dw-mshc-hs400-timing:
75 The value of CIU TX and RX clock phase shift value for HS400 mode
97 See also samsung,dw-mshc-hs400-timing property.
102 RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
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| D | mmc-controller.yaml | 215 mmc-hs400-1_2v:
218 eMMC HS400 mode (1.2V I/O) is supported.
220 mmc-hs400-1_8v:
223 eMMC HS400 mode (1.8V I/O) is supported.
225 mmc-hs400-enhanced-strobe:
228 eMMC HS400 enhanced strobe mode is supported
230 no-mmc-hs400:
233 All eMMC HS400 modes are not supported.
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| D | cdns,sdhci.yaml | 95 HS200, HS400 and HS400_ES.
102 Value of the delay introduced on the sdclk output for HS200, HS400 and
111 HS400 / HS400_ES speed modes.
154 mmc-hs400-1_8v;
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| D | sdhci-sprd.txt | 40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
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| D | sdhci-am654.yaml | 121 ti,otap-del-sel-hs400:
122 description: Output tap delay for eMMC HS400 timing
190 description: strobe select delay for HS400 speed mode.
236 ti,otap-del-sel-hs400 = <0x0>;
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| D | brcm,sdhci-brcmstb.yaml | 110 mmc-hs400-1_8v;
111 mmc-hs400-enhanced-strobe;
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| D | sdhci-acpi.c | 497 * while HS400 tuning is in progress we end up with mismatched driver in amd_select_drive_strength()
498 * strengths between the controller and the card. HS400 tuning requires in amd_select_drive_strength()
499 * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch in amd_select_drive_strength()
507 * card's timing to HS200 or HS400. The card will use the default driver in amd_select_drive_strength()
528 * The initialization sequence for HS400 is:
529 * HS->HS200->Perform Tuning->HS->HS400
532 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
534 * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
537 * HS400, we can re-enable the tuned clock.
562 /* DLL is only required for HS400 */ in amd_set_ios()
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| D | renesas_sdhi.h | 17 u32 tap; /* sampling clock position for SDR104/HS400 (8 TAP) */
18 u32 tap_hs400_4tap; /* sampling clock position for HS400 (4 TAP) */
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-acpi.c | 569 * The initialization sequence for HS400 is:
570 * HS->HS200->Perform Tuning->HS->HS400
573 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
575 * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
578 * HS400, we can re-enable the tuned clock.
603 /* DLL is only required for HS400 */ in amd_set_ios()
673 * b) The HS200 and HS400 driver strengths don't match. in sdhci_acpi_emmc_amd_probe_slot()
675 * A, but the (internal) HS400 preset register has a driver in sdhci_acpi_emmc_amd_probe_slot()
676 * strength of B. As part of initializing HS400, HS200 tuning in sdhci_acpi_emmc_amd_probe_slot()
683 * HS400 preset driver strengths match. in sdhci_acpi_emmc_amd_probe_slot()
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| D | renesas_sdhi.h | 17 u32 tap; /* sampling clock position for SDR104/HS400 (8 TAP) */
18 u32 tap_hs400_4tap; /* sampling clock position for HS400 (4 TAP) */
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/ |
| D | exynos7885-jackpotlte.dts | 67 mmc-hs400-1_8v;
70 mmc-hs400-enhanced-strobe;
77 samsung,dw-mshc-hs400-timing = <0 2>;
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| D | exynos850-e850-96.dts | 140 mmc-hs400-1_8v;
143 mmc-hs400-enhanced-strobe;
150 samsung,dw-mshc-hs400-timing = <0 2>;
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt7986a-bananapi-bpi-r3-emmc.dtso | 20 mmc-hs400-1_8v;
21 hs400-ds-delay = <0x14014>;
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3588-edgeble-neu6a.dtsi | 28 mmc-hs400-1_8v;
29 mmc-hs400-enhanced-strobe;
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| D | rk3588s-khadas-edge2.dts | 28 mmc-hs400-1_8v;
29 mmc-hs400-enhanced-strobe;
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