| /kernel/linux/linux-5.10/drivers/mailbox/ |
| D | stm32-ipcc.c | 53 spinlock_t lock; /* protect access to IPCC registers */
83 struct stm32_ipcc *ipcc = data; in stm32_ipcc_rx_irq() local
84 struct device *dev = ipcc->controller.dev; in stm32_ipcc_rx_irq()
90 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; in stm32_ipcc_rx_irq()
91 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_rx_irq()
92 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq()
97 for (chan = 0; chan < ipcc->n_chans; chan++) { in stm32_ipcc_rx_irq()
103 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL); in stm32_ipcc_rx_irq()
105 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, in stm32_ipcc_rx_irq()
116 struct stm32_ipcc *ipcc = data; in stm32_ipcc_tx_irq() local
[all …]
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| D | qcom-ipcc.c | 14 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 /* IPCC Register offsets */
44 * @base: Base address of the IPCC frame associated to APSS
74 struct qcom_ipcc *ipcc = data; in qcom_ipcc_irq_fn() local
79 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); in qcom_ipcc_irq_fn()
83 virq = irq_find_mapping(ipcc->irq_domain, hwirq); in qcom_ipcc_irq_fn()
84 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); in qcom_ipcc_irq_fn()
93 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); in qcom_ipcc_mask_irq() local
96 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); in qcom_ipcc_mask_irq()
101 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); in qcom_ipcc_unmask_irq() local
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| D | Kconfig | 203 tristate "STM32 IPCC Mailbox"
207 with hardware for Inter-Processor Communication Controller (IPCC)
248 bool "Qualcomm Technologies, Inc. IPCC driver"
252 (IPCC) driver for MSM devices. The driver provides mailbox support for
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| /kernel/linux/linux-6.6/drivers/mailbox/ |
| D | stm32-ipcc.c | 54 spinlock_t lock; /* protect access to IPCC registers */
84 struct stm32_ipcc *ipcc = data; in stm32_ipcc_rx_irq() local
85 struct device *dev = ipcc->controller.dev; in stm32_ipcc_rx_irq()
91 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; in stm32_ipcc_rx_irq()
92 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_rx_irq()
93 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq()
98 for (chan = 0; chan < ipcc->n_chans; chan++) { in stm32_ipcc_rx_irq()
104 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL); in stm32_ipcc_rx_irq()
106 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, in stm32_ipcc_rx_irq()
117 struct stm32_ipcc *ipcc = data; in stm32_ipcc_tx_irq() local
[all …]
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| D | qcom-ipcc.c | 14 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 /* IPCC Register offsets */
42 * @base: Base address of the IPCC frame associated to APSS
74 struct qcom_ipcc *ipcc = data; in qcom_ipcc_irq_fn() local
79 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); in qcom_ipcc_irq_fn()
83 virq = irq_find_mapping(ipcc->irq_domain, hwirq); in qcom_ipcc_irq_fn()
84 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); in qcom_ipcc_irq_fn()
93 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); in qcom_ipcc_mask_irq() local
96 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); in qcom_ipcc_mask_irq()
101 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); in qcom_ipcc_unmask_irq() local
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/ |
| D | qcom-ipcc.yaml | 4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
20 protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
27 - qcom,qdu1000-ipcc
28 - qcom,sa8775p-ipcc
29 - qcom,sc7280-ipcc
30 - qcom,sc8280xp-ipcc
31 - qcom,sm6350-ipcc
32 - qcom,sm6375-ipcc
33 - qcom,sm8250-ipcc
[all …]
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| D | st,stm32-ipcc.yaml | 4 $id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#
10 The IPCC block provides a non blocking signaling mechanism to post and
21 const: st,stm32mp1-ipcc
64 ipcc: mailbox@4c001000 {
65 compatible = "st,stm32mp1-ipcc";
72 clocks = <&rcc_clk IPCC>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | qcom-ipcc.yaml | 4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
20 protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
27 - qcom,sm8250-ipcc
28 - const: qcom,ipcc
62 #include <dt-bindings/mailbox/qcom-ipcc.h>
65 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
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| D | st,stm32-ipcc.yaml | 4 $id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
10 The IPCC block provides a non blocking signaling mechanism to post and
21 const: st,stm32mp1-ipcc
70 ipcc: mailbox@4c001000 {
71 compatible = "st,stm32mp1-ipcc";
79 clocks = <&rcc_clk IPCC>;
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| /kernel/linux/linux-5.10/sound/soc/intel/catpt/ |
| D | ipc.c | 64 catpt_writel_shim(cdev, IPCC, header); in catpt_dsp_send_tx()
268 u32 isc, ipcc; in catpt_dsp_irq_handler() local
278 ipcc = catpt_readl_shim(cdev, IPCC); in catpt_dsp_irq_handler()
279 trace_catpt_ipc_reply(ipcc); in catpt_dsp_irq_handler()
280 catpt_dsp_copy_rx(cdev, ipcc); in catpt_dsp_irq_handler()
284 catpt_updatel_shim(cdev, IPCC, CATPT_IPCC_DONE, 0); in catpt_dsp_irq_handler()
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| /kernel/linux/linux-6.6/sound/soc/intel/catpt/ |
| D | ipc.c | 64 catpt_writel_shim(cdev, IPCC, header); in catpt_dsp_send_tx()
268 u32 isc, ipcc; in catpt_dsp_irq_handler() local
278 ipcc = catpt_readl_shim(cdev, IPCC); in catpt_dsp_irq_handler()
279 trace_catpt_ipc_reply(ipcc); in catpt_dsp_irq_handler()
280 catpt_dsp_copy_rx(cdev, ipcc); in catpt_dsp_irq_handler()
284 catpt_updatel_shim(cdev, IPCC, CATPT_IPCC_DONE, 0); in catpt_dsp_irq_handler()
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/st/ |
| D | stm32mp157a-microgea-stm32mp1.dtsi | 116 &ipcc {
128 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| D | stm32mp15xx-osd32.dtsi | 206 &ipcc {
213 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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| D | stm32mp157c-odyssey-som.dtsi | 221 &ipcc {
233 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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| D | stm32mp15xx-dhcor-som.dtsi | 218 &ipcc {
230 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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| D | stm32mp157a-icore-stm32mp1.dtsi | 164 &ipcc {
176 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| D | stm32mp157c-ed1.dts | 305 &ipcc {
317 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,glink-edge.yaml | 81 #include <dt-bindings/mailbox/qcom-ipcc.h>
88 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
91 mboxes = <&ipcc IPCC_CLIENT_WPSS
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| D | qcom,sc8280xp-pas.yaml | 105 #include <dt-bindings/mailbox/qcom-ipcc.h>
137 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
140 mboxes = <&ipcc IPCC_CLIENT_LPASS
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| D | qcom,sm6350-pas.yaml | 128 #include <dt-bindings/mailbox/qcom-ipcc.h>
157 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
160 mboxes = <&ipcc IPCC_CLIENT_LPASS
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| D | qcom,sm8550-pas.yaml | 138 #include <dt-bindings/mailbox/qcom-ipcc.h>
169 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
172 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
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| D | qcom,sm8350-pas.yaml | 142 #include <dt-bindings/mailbox/qcom-ipcc.h>
173 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
176 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | stm32mp15xx-osd32.dtsi | 211 &ipcc {
218 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| D | stm32mp157c-odyssey-som.dtsi | 231 &ipcc {
243 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/misc/ |
| D | qcom,fastrpc.yaml | 107 #include <dt-bindings/mailbox/qcom-ipcc.h>
110 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
113 mboxes = <&ipcc IPCC_CLIENT_LPASS
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