| /kernel/linux/linux-6.6/drivers/counter/ |
| D | interrupt-cnt.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/irq.h>
17 #define INTERRUPT_CNT_NAME "interrupt-cnt"
22 int irq; member
25 struct counter_signal signals; member
30 static irqreturn_t interrupt_cnt_isr(int irq, void *dev_id) in interrupt_cnt_isr() argument
35 atomic_inc(&priv->count); in interrupt_cnt_isr()
47 guard(mutex)(&priv->lock); in interrupt_cnt_enable_read()
49 *enable = priv->enabled; in interrupt_cnt_enable_read()
59 guard(mutex)(&priv->lock); in interrupt_cnt_enable_write()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/ |
| D | intel_breadcrumbs.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2015-2021 Intel Corporation
21 return intel_engine_irq_enable(b->irq_engine); in irq_enable()
26 intel_engine_irq_disable(b->irq_engine); in irq_disable()
35 if (GEM_WARN_ON(!intel_gt_pm_get_if_awake(b->irq_engine->gt))) in __intel_breadcrumbs_arm_irq()
39 * The breadcrumb irq will be disarmed on the interrupt after the in __intel_breadcrumbs_arm_irq()
41 * which we can add a new waiter and avoid the cost of re-enabling in __intel_breadcrumbs_arm_irq()
42 * the irq. in __intel_breadcrumbs_arm_irq()
44 WRITE_ONCE(b->irq_armed, true); in __intel_breadcrumbs_arm_irq()
47 if (!b->irq_enabled++ && b->irq_enable(b)) in __intel_breadcrumbs_arm_irq()
[all …]
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| /kernel/linux/linux-6.6/arch/um/os-Linux/ |
| D | signal.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Anton Ivanov (aivanov@{brocade.com,kot-begemot.co.uk})
6 * Copyright (C) 2004 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
16 #include <as-layout.h>
46 /* enable signals if sig isn't IRQ signal */ in sig_handler_common()
56 * These are the asynchronous signals. SIGPROF is excluded because we want to
57 * be able to profile all of UML, not just the non-critical sections. If
58 * profiling is not thread-safe, then that is not my problem. We can disable
91 * In TT_MODE_EXTERNAL, need to still call time-travel in sig_handler()
94 * Note we won't get here if signals are hard-blocked in sig_handler()
[all …]
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| /kernel/linux/linux-5.10/arch/um/os-Linux/ |
| D | signal.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Anton Ivanov (aivanov@{brocade.com,kot-begemot.co.uk})
6 * Copyright (C) 2004 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
15 #include <as-layout.h>
44 /* enable signals if sig isn't IRQ signal */ in sig_handler_common()
54 * These are the asynchronous signals. SIGPROF is excluded because we want to
55 * be able to profile all of UML, not just the non-critical sections. If
56 * profiling is not thread-safe, then that is not my problem. We can disable
132 .ss_size = size - sizeof(void *) in set_sigstack()
166 mcontext_t *mc = &uc->uc_mcontext; in hard_handler()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | intel_breadcrumbs.c | 39 if (!engine->irq_enable) in irq_enable()
43 spin_lock(&engine->gt->irq_lock); in irq_enable()
44 engine->irq_enable(engine); in irq_enable()
45 spin_unlock(&engine->gt->irq_lock); in irq_enable()
52 if (!engine->irq_disable) in irq_disable()
56 spin_lock(&engine->gt->irq_lock); in irq_disable()
57 engine->irq_disable(engine); in irq_disable()
58 spin_unlock(&engine->gt->irq_lock); in irq_disable()
67 if (GEM_WARN_ON(!intel_gt_pm_get_if_awake(b->irq_engine->gt))) in __intel_breadcrumbs_arm_irq()
71 * The breadcrumb irq will be disarmed on the interrupt after the in __intel_breadcrumbs_arm_irq()
[all …]
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| /kernel/linux/linux-5.10/drivers/tty/ |
| D | synclink_gt.c | 1 // SPDX-License-Identifier: GPL-1.0+
28 * DBGINFO information - most verbose output
76 #include <asm/irq.h>
147 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
255 bool irq_requested; /* true if IRQ requested */
287 unsigned char signals; /* serial signal states */ member
500 printk("%s %s data:\n",info->device_name, label); in trace_block()
515 count -= linecount; in trace_block()
526 printk("tbuf_current=%d\n", info->tbuf_current); in dump_tbufs()
527 for (i=0 ; i < info->tbuf_count ; i++) { in dump_tbufs()
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| /kernel/linux/linux-6.6/drivers/tty/ |
| D | synclink_gt.c | 1 // SPDX-License-Identifier: GPL-1.0+
28 * DBGINFO information - most verbose output
76 #include <asm/irq.h>
145 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
251 bool irq_requested; /* true if IRQ requested */
283 unsigned char signals; /* serial signal states */ member
495 printk("%s %s data:\n",info->device_name, label); in trace_block()
510 count -= linecount; in trace_block()
521 printk("tbuf_current=%d\n", info->tbuf_current); in dump_tbufs()
522 for (i=0 ; i < info->tbuf_count ; i++) { in dump_tbufs()
[all …]
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-mtk-cirq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/irq.h>
42 struct mtk_cirq_chip_data *chip_data = data->chip_data; in mtk_cirq_write_mask()
43 unsigned int cirq_num = data->hwirq; in mtk_cirq_write_mask()
46 writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4); in mtk_cirq_write_mask()
86 data = data->parent_data; in mtk_cirq_set_type()
87 ret = data->chip->irq_set_type(data, type); in mtk_cirq_set_type()
108 if (is_of_node(fwspec->fwnode)) { in mtk_cirq_domain_translate()
109 if (fwspec->param_count != 3) in mtk_cirq_domain_translate()
110 return -EINVAL; in mtk_cirq_domain_translate()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/driver-api/gpio/ |
| D | legacy.rst | 13 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
21 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
22 non-dedicated pin can be configured as a GPIO; and most chips have at least
27 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
32 - Output values are writable (high=1, low=0). Some chips also have
34 value might be driven ... supporting "wire-OR" and similar schemes
37 - Input values are likewise readable (1, 0). Some chips support readback
38 of pins configured as "output", which is very useful in such "wire-OR"
40 input de-glitch/debounce logic, sometimes with software controls.
42 - Inputs can often be used as IRQ signals, often edge triggered but
[all …]
|
| D | intro.rst | 16 - The descriptor-based interface is the preferred way to manipulate GPIOs,
18 - The legacy integer-based interface which is considered deprecated (but still
21 The remainder of this document applies to the new descriptor-based interface.
23 integer-based interface.
29 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
37 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
38 non-dedicated pin can be configured as a GPIO; and most chips have at least
43 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
48 - Output values are writable (high=1, low=0). Some chips also have
50 value might be driven, supporting "wire-OR" and similar schemes for the
[all …]
|
| /kernel/linux/linux-5.10/Documentation/driver-api/gpio/ |
| D | legacy.rst | 13 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
21 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
22 non-dedicated pin can be configured as a GPIO; and most chips have at least
27 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
32 - Output values are writable (high=1, low=0). Some chips also have
34 value might be driven ... supporting "wire-OR" and similar schemes
37 - Input values are likewise readable (1, 0). Some chips support readback
38 of pins configured as "output", which is very useful in such "wire-OR"
40 input de-glitch/debounce logic, sometimes with software controls.
42 - Inputs can often be used as IRQ signals, often edge triggered but
[all …]
|
| D | intro.rst | 16 - The descriptor-based interface is the preferred way to manipulate GPIOs,
17 and is described by all the files in this directory excepted gpio-legacy.txt.
18 - The legacy integer-based interface which is considered deprecated (but still
19 usable for compatibility reasons) is documented in gpio-legacy.txt.
21 The remainder of this document applies to the new descriptor-based interface.
22 gpio-legacy.txt contains the same information applied to the legacy
23 integer-based interface.
29 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
37 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
38 non-dedicated pin can be configured as a GPIO; and most chips have at least
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
[all …]
|
| /kernel/linux/linux-5.10/drivers/platform/mellanox/ |
| D | mlxreg-hotplug.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2016-2020 Mellanox Technologies
11 #include <linux/hwmon-sysfs.h>
35 * struct mlxreg_hotplug_priv_data - platform private data:
36 * @irq: platform device interrupt number;
55 int irq; member
86 string_upper(label, data->label); in mlxreg_hotplug_udev_event_send()
99 mlxreg_hotplug_udev_event_send(&priv->hwmon->kobj, data, true); in mlxreg_hotplug_device_create()
105 if (data->hpdev.nr < 0) in mlxreg_hotplug_device_create()
108 pdata = dev_get_platdata(&priv->pdev->dev); in mlxreg_hotplug_device_create()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
16 connect control signals from SFP modules and to act as an LED
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
[all …]
|
| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-mtk-cirq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/irq.h>
71 return chip_data->base + chip_data->offsets[idx]; in mtk_cirq_reg()
83 struct mtk_cirq_chip_data *chip_data = data->chip_data; in mtk_cirq_write_mask()
84 unsigned int cirq_num = data->hwirq; in mtk_cirq_write_mask()
127 data = data->parent_data; in mtk_cirq_set_type()
128 ret = data->chip->irq_set_type(data, type); in mtk_cirq_set_type()
149 if (is_of_node(fwspec->fwnode)) { in mtk_cirq_domain_translate()
150 if (fwspec->param_count != 3) in mtk_cirq_domain_translate()
151 return -EINVAL; in mtk_cirq_domain_translate()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-eic-sprd.c | 1 // SPDX-License-Identifier: GPL-2.0
53 * The digital-chip EIC controller can support maximum 3 banks, and each bank
59 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
64 * input mode to generate interrupts if detecting input signals.
66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
69 * The debounce EIC is used to capture the input signals' stable status
70 * (millisecond resolution) and a single-trigger mechanism is introduced
71 * into this sub-module to enhance the input event detection reliability.
74 * The latch EIC is used to latch some special power down signals and
76 * to capture signals.
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpio/ |
| D | gpio-eic-sprd.c | 1 // SPDX-License-Identifier: GPL-2.0
53 * The digital-chip EIC controller can support maximum 3 banks, and each bank
59 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
64 * input mode to generate interrupts if detecting input signals.
66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
69 * The debounce EIC is used to capture the input signals' stable status
70 * (millisecond resolution) and a single-trigger mechanism is introduced
71 * into this sub-module to enhance the input event detection reliability.
74 * The latch EIC is used to latch some special power down signals and
76 * to capture signals.
[all …]
|
| /kernel/linux/linux-6.6/drivers/platform/mellanox/ |
| D | mlxreg-hotplug.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2016-2020 Mellanox Technologies
11 #include <linux/hwmon-sysfs.h>
34 * struct mlxreg_hotplug_priv_data - platform private data:
35 * @irq: platform device interrupt number;
54 int irq; member
85 string_upper(label, data->label); in mlxreg_hotplug_udev_event_send()
97 dev_pdata->regmap = regmap; in mlxreg_hotplug_pdata_export()
104 struct i2c_board_info *brdinfo = data->hpdev.brdinfo; in mlxreg_hotplug_device_create()
109 mlxreg_hotplug_udev_event_send(&priv->hwmon->kobj, data, true); in mlxreg_hotplug_device_create()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.txt | 10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
48 Each GPIO controller can generate a number of interrupt signals. Each signal
50 number of interrupt signals generated by a controller varies as a rough function
52 both the overall controller HW module and the sets-of-ports as "controllers".
54 Each GPIO controller in fact generates multiple interrupts signals for each set
56 interrupt signals generated by a set-of-ports. The intent is for each generated
59 per-port-set signals is reported via a separate register. Thus, a driver needs
[all …]
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| /kernel/linux/linux-5.10/arch/m68k/mac/ |
| D | macints.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * exclusively use the autovector interrupts (the 'generic level0-level7'
8 * interrupts with exception vectors 0x19-0x1f). The following interrupt levels
10 * 1 - VIA1
11 * - slot 0: one second interrupt (CA2)
12 * - slot 1: VBlank (CA1)
13 * - slot 2: ADB data ready (SR full)
14 * - slot 3: ADB data (CB2)
15 * - slot 4: ADB clock (CB1)
16 * - slot 5: timer 2
[all …]
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| /kernel/linux/linux-6.6/arch/m68k/mac/ |
| D | macints.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * exclusively use the autovector interrupts (the 'generic level0-level7'
8 * interrupts with exception vectors 0x19-0x1f). The following interrupt levels
10 * 1 - VIA1
11 * - slot 0: one second interrupt (CA2)
12 * - slot 1: VBlank (CA1)
13 * - slot 2: ADB data ready (SR full)
14 * - slot 3: ADB data (CB2)
15 * - slot 4: ADB clock (CB1)
16 * - slot 5: timer 2
[all …]
|
| /kernel/linux/linux-5.10/drivers/parisc/ |
| D | iosapic_private.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
7 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
15 ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
21 ** -----------------------
24 ** table per cell. N- and L-class consist of a single cell.
42 ** Polarity of SAPIC I/O input signals:
47 ** Trigger mode of SAPIC I/O input signals:
49 ** 01 = Edge-triggered
51 ** 11 = Level-triggered
[all …]
|
| /kernel/linux/linux-6.6/drivers/parisc/ |
| D | iosapic_private.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
7 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
15 ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
21 ** -----------------------
24 ** table per cell. N- and L-class consist of a single cell.
42 ** Polarity of SAPIC I/O input signals:
47 ** Trigger mode of SAPIC I/O input signals:
49 ** 01 = Edge-triggered
51 ** 11 = Level-triggered
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,keystone-irq.txt | 1 Keystone 2 IRQ controller IP
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
5 The IRQ handler running on HOST OS can identify DSP signal source by
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
24 compatible = "ti,keystone-irq";
25 ti,syscon-dev = <&devctrl 0x2a0>;
[all …]
|