| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/ |
| D | freescale-l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen4/ |
| D | cache.json | 5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all…
11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har…
17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all…
23 "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
35 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the…
41 "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
47 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d…
53 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa…
59 "BriefDescription": "Demand data cache fills from extension memory.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
20 …escription": "The number of 64 byte instruction cache line fulfilled from system memory or another…
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 … due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC ev…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …tch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheab…
15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
20 …escription": "The number of 64 byte instruction cache line fulfilled from system memory or another…
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …"IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cach…
64 … due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC ev…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /kernel/linux/linux-5.10/arch/loongarch/boot/dts/loongson/ |
| D | loongson3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson-3 may have as many as 4 nodes, each node has 4 cores.
8 #address-cells = <1>;
9 #size-cells = <0>;
15 l2-cache = <&vcache0>;
16 next-level-cache = <&scache0>;
23 l2-cache = <&vcache1>;
24 next-level-cache = <&scache0>;
31 l2-cache = <&vcache2>;
32 next-level-cache = <&scache0>;
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 10 "BriefDescription": "L1 Cache evictions for dirty data",
13 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
18 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
21 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
33 "BriefDescription": "L2 cache request misses",
36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
41 "BriefDescription": "L2 cache requests",
44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
54 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
10 "BriefDescription": "L2 cache request misses"
14 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
20 "BriefDescription": "L2 cache requests"
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
44 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
50 "BriefDescription": "L1 Cache evictions for dirty data"
54 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
60 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
86 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | cache.json | 10 "BriefDescription": "L1 Cache evictions for dirty data",
13 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
18 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
21 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
33 "BriefDescription": "L2 cache request misses",
36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
41 "BriefDescription": "L2 cache requests",
44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
54 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit…
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| D | cache.json | 3 …"PublicDescription": "L1 instruction cache refill. This event counts any instruction fetch which m…
6 "BriefDescription": "L1 instruction cache refill"
9 …LB refill. This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes r…
15 …"PublicDescription": "L1 data cache refill. This event counts any load or store operation or page …
18 "BriefDescription": "L1 data cache refill"
21 …tion": "L1 data cache access. This event counts any load or store operation or page table walk acc…
24 "BriefDescription": "L1 data cache access"
27 … data TLB refill. This event counts any refill of the data L1 TLB from the L2 TLB. This includes r…
33 …on cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which ac…
36 "BriefDescription": "L1 instruction cache access"
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| D | cache.json | 102 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev…
105 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev…
108 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that…
111 …": "L1 data cache refill due to prefetch. This event counts any linefills from the prefetcher that…
114 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami…
117 …L2 cache write streaming mode. This event counts for each cycle where the core is in write streami…
120 …"PublicDescription": "L1 data cache entering write streaming mode. This event counts for each entr…
123 …"BriefDescription": "L1 data cache entering write streaming mode. This event counts for each entry…
126 …cache write streaming mode. This event counts for each cycle where the core is in write streaming …
129 …cache write streaming mode. This event counts for each cycle where the core is in write streaming …
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | cache.json | 4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
12 "BriefDescription": "L2 cache request misses"
16 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
24 "BriefDescription": "L2 cache requests"
28 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
52 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
60 "BriefDescription": "L1 Cache evictions for dirty data"
64 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
72 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss."
101 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | cache.json | 6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
22 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
45 "BriefDescription": "Not rejected writebacks that hit L2 cache",
48 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
53 "BriefDescription": "L2 cache lines filling L2",
56 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
61 "BriefDescription": "L2 cache lines in E state filling L2",
64 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
69 "BriefDescription": "L2 cache lines in I state filling L2",
72 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | cache.json | 3 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
29 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
32 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
40 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
54 "BriefDescription": "L2 cache lines filling L2",
57 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
62 …"BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cac…
65 …iption": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fi…
70 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | cache.json | 6 "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
69 …iption": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from…
77 "BriefDescription": "L2 cache lines filling L2",
80 "PublicDescription": "L2 cache lines filling L2.",
85 "BriefDescription": "L2 cache lines in E state filling L2",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | cache.json | 6 …en new data lines are brought into the L1 Data cache, which cause other lines to be evicted from t…
51 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
67 "BriefDescription": "L2 cache lines in E state filling L2",
70 "PublicDescription": "L2 cache lines in E state filling L2.",
75 "BriefDescription": "L2 cache lines in I state filling L2",
78 "PublicDescription": "L2 cache lines in I state filling L2.",
83 "BriefDescription": "L2 cache lines in S state filling L2",
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/sysdev/ |
| D | fsl_85xx_l2ctlr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
5 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
27 return -EINVAL; in get_cache_sram_params()
30 return -EINVAL; in get_cache_sram_params()
32 sram_params->sram_offset = addr; in get_cache_sram_params()
33 sram_params->sram_size = size; in get_cache_sram_params()
56 __setup("cache-sram-size=", get_size_from_cmdline);
57 __setup("cache-sram-offset=", get_offset_from_cmdline);
68 if (!dev->dev.of_node) { in mpc85xx_l2ctlr_of_probe()
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/haswell/ |
| D | cache.json | 6 …en new data lines are brought into the L1 Data cache, which cause other lines to be evicted from t…
51 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
67 "BriefDescription": "L2 cache lines in E state filling L2",
70 "PublicDescription": "L2 cache lines in E state filling L2.",
75 "BriefDescription": "L2 cache lines in I state filling L2",
78 "PublicDescription": "L2 cache lines in I state filling L2.",
83 "BriefDescription": "L2 cache lines in S state filling L2",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| D | cache.json | 3 …ts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a…
6 …L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L…
21 …The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 …
25 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
28 … "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door request…
32 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe…
35 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d…
40 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p…
43 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front …
48 …"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Cou…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | cache.json | 3 …ts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a…
6 …L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L…
21 …The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 …
25 … "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.",
28 … "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door request…
32 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a pe…
35 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front d…
40 …"BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a p…
43 …"PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front …
48 …"BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Cou…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | cache.json | 10 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
13 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
44 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
47 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
55 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
69 "BriefDescription": "L2 cache lines filling L2",
72 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
84 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
87 …re silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in S…
92 …"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand acce…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
[all …]
|