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/kernel/linux/linux-6.6/drivers/isdn/mISDN/
Dlayer2.c92 struct layer2 *l2 = fi->userdata; in l2m_debug() local
104 printk(KERN_DEBUG "%s l2 (sapi %d tei %d): %pV\n", in l2m_debug()
105 mISDNDevName4ch(&l2->ch), l2->sapi, l2->tei, &vaf); in l2m_debug()
111 l2headersize(struct layer2 *l2, int ui) in l2headersize() argument
113 return ((test_bit(FLG_MOD128, &l2->flag) && (!ui)) ? 2 : 1) + in l2headersize()
114 (test_bit(FLG_LAPD, &l2->flag) ? 2 : 1); in l2headersize()
118 l2addrsize(struct layer2 *l2) in l2addrsize() argument
120 return test_bit(FLG_LAPD, &l2->flag) ? 2 : 1; in l2addrsize()
124 l2_newid(struct layer2 *l2) in l2_newid() argument
128 id = l2->next_id++; in l2_newid()
[all …]
Dtei.c109 struct layer2 *l2; in da_deactivate() local
113 list_for_each_entry(l2, &mgr->layer2, list) { in da_deactivate()
114 if (l2->l2m.state > ST_L2_4) { in da_deactivate()
146 struct layer2 *l2; in da_timer() local
151 list_for_each_entry(l2, &mgr->layer2, list) { in da_timer()
152 if (l2->l2m.state > ST_L2_4) { in da_timer()
234 tm->l2->sapi, tm->l2->tei, &vaf); in tei_debug()
246 struct layer2 *l2; in get_free_id() local
248 list_for_each_entry(l2, &mgr->layer2, list) { in get_free_id()
249 if (l2->ch.nr > 63) { in get_free_id()
[all …]
/kernel/linux/linux-5.10/drivers/isdn/mISDN/
Dlayer2.c92 struct layer2 *l2 = fi->userdata; in l2m_debug() local
104 printk(KERN_DEBUG "%s l2 (sapi %d tei %d): %pV\n", in l2m_debug()
105 mISDNDevName4ch(&l2->ch), l2->sapi, l2->tei, &vaf); in l2m_debug()
111 l2headersize(struct layer2 *l2, int ui) in l2headersize() argument
113 return ((test_bit(FLG_MOD128, &l2->flag) && (!ui)) ? 2 : 1) + in l2headersize()
114 (test_bit(FLG_LAPD, &l2->flag) ? 2 : 1); in l2headersize()
118 l2addrsize(struct layer2 *l2) in l2addrsize() argument
120 return test_bit(FLG_LAPD, &l2->flag) ? 2 : 1; in l2addrsize()
124 l2_newid(struct layer2 *l2) in l2_newid() argument
128 id = l2->next_id++; in l2_newid()
[all …]
Dtei.c109 struct layer2 *l2; in da_deactivate() local
113 list_for_each_entry(l2, &mgr->layer2, list) { in da_deactivate()
114 if (l2->l2m.state > ST_L2_4) { in da_deactivate()
146 struct layer2 *l2; in da_timer() local
151 list_for_each_entry(l2, &mgr->layer2, list) { in da_timer()
152 if (l2->l2m.state > ST_L2_4) { in da_timer()
234 tm->l2->sapi, tm->l2->tei, &vaf); in tei_debug()
246 struct layer2 *l2; in get_free_id() local
248 list_for_each_entry(l2, &mgr->layer2, list) { in get_free_id()
249 if (l2->ch.nr > 63) { in get_free_id()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dl2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
15 "fsl,b4420-l2-cache-controller"
16 "fsl,b4860-l2-cache-controller"
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/
Dfreescale-l2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
16 "fsl,mpc8541-l2-cache-controller"
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen4/
Dcache.json23 "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
71 "BriefDescription": "Any data cache fills from local L2 cache.",
77 "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
83 …"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in…
149 …move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
191 "BriefDescription": "Software prefetch data cache fills from local L2 cache.",
197 …"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the…
239 "BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
245 …"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the…
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen1/
Dcache.json15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
58 …"BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
105 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen1/
Dcache.json15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
58 …"BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
105 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
[all …]
/kernel/linux/linux-5.10/drivers/memory/
Dbt1-l2-ctl.c8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
77 static int l2_ctl_get_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 *val) in l2_ctl_get_latency() argument
82 ret = regmap_read(l2->sys_regs, L2_CTL_REG, &data); in l2_ctl_get_latency()
103 static int l2_ctl_set_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 val) in l2_ctl_set_latency() argument
130 ret = regmap_update_bits(l2->sys_regs, L2_CTL_REG, mask, data); in l2_ctl_set_latency()
134 return regmap_read_poll_timeout(l2->sys_regs, L2_CTL_REG, data, in l2_ctl_set_latency()
[all …]
/kernel/linux/linux-6.6/drivers/memory/
Dbt1-l2-ctl.c8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
77 static int l2_ctl_get_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 *val) in l2_ctl_get_latency() argument
82 ret = regmap_read(l2->sys_regs, L2_CTL_REG, &data); in l2_ctl_get_latency()
103 static int l2_ctl_set_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 val) in l2_ctl_set_latency() argument
130 ret = regmap_update_bits(l2->sys_regs, L2_CTL_REG, mask, data); in l2_ctl_set_latency()
134 return regmap_read_poll_timeout(l2->sys_regs, L2_CTL_REG, data, in l2_ctl_set_latency()
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen2/
Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen2/
Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen3/
Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/bonnell/
Dcache.json52 "BriefDescription": "Cycles L2 address bus is in use.",
94 "BriefDescription": "Cycles the L2 cache data bus is busy.",
101 "BriefDescription": "Cycles the L2 transfers data to the core.",
108 "BriefDescription": "L2 cacheable instruction fetch requests",
115 "BriefDescription": "L2 cacheable instruction fetch requests",
122 "BriefDescription": "L2 cacheable instruction fetch requests",
129 "BriefDescription": "L2 cacheable instruction fetch requests",
136 "BriefDescription": "L2 cacheable instruction fetch requests",
143 "BriefDescription": "L2 cache reads",
150 "BriefDescription": "L2 cache reads",
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/bonnell/
Dcache.json8 "BriefDescription": "Cycles L2 address bus is in use."
16 "BriefDescription": "Cycles the L2 cache data bus is busy."
24 "BriefDescription": "Cycles the L2 transfers data to the core."
32 "BriefDescription": "L2 cache misses."
40 "BriefDescription": "L2 cache misses."
48 "BriefDescription": "L2 cache misses."
56 "BriefDescription": "L2 cache line modifications."
64 "BriefDescription": "L2 cache lines evicted."
72 "BriefDescription": "L2 cache lines evicted."
80 "BriefDescription": "L2 cache lines evicted."
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/goldmont/
Dcache.json29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
33 "BriefDescription": "L2 cache request misses",
36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
41 "BriefDescription": "L2 cache requests",
44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
54 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
89 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
94 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
99 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
104 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/goldmontplus/
Dcache.json29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
33 "BriefDescription": "L2 cache request misses",
36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
41 "BriefDescription": "L2 cache requests",
44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
54 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
89 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
94 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
99 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
104 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmont/
Dcache.json4 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
10 "BriefDescription": "L2 cache request misses"
14 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
20 "BriefDescription": "L2 cache requests"
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
170 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
176 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
194 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
200 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
230 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
[all …]
/kernel/linux/linux-5.10/arch/loongarch/boot/dts/loongson/
Dloongson3.dtsi15 l2-cache = <&vcache0>;
23 l2-cache = <&vcache1>;
31 l2-cache = <&vcache2>;
39 l2-cache = <&vcache3>;
47 l2-cache = <&vcache4>;
55 l2-cache = <&vcache5>;
63 l2-cache = <&vcache6>;
71 l2-cache = <&vcache7>;
79 l2-cache = <&vcache8>;
87 l2-cache = <&vcache9>;
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/broadwellde/
Dcache.json45 "BriefDescription": "Not rejected writebacks that hit L2 cache",
48 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
53 "BriefDescription": "L2 cache lines filling L2",
56 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
61 "BriefDescription": "L2 cache lines in E state filling L2",
64 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
69 "BriefDescription": "L2 cache lines in I state filling L2",
72 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
77 "BriefDescription": "L2 cache lines in S state filling L2",
80 …ublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the…
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/ivybridge/
Dcache.json46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
69 …"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-reject…
77 "BriefDescription": "L2 cache lines filling L2",
80 "PublicDescription": "L2 cache lines filling L2.",
85 "BriefDescription": "L2 cache lines in E state filling L2",
88 "PublicDescription": "L2 cache lines in E state filling L2.",
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/haswellx/
Dcache.json51 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
67 "BriefDescription": "L2 cache lines in E state filling L2",
70 "PublicDescription": "L2 cache lines in E state filling L2.",
75 "BriefDescription": "L2 cache lines in I state filling L2",
78 "PublicDescription": "L2 cache lines in I state filling L2.",
83 "BriefDescription": "L2 cache lines in S state filling L2",
86 "PublicDescription": "L2 cache lines in S state filling L2.",
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/haswell/
Dcache.json51 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
62 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
67 "BriefDescription": "L2 cache lines in E state filling L2",
70 "PublicDescription": "L2 cache lines in E state filling L2.",
75 "BriefDescription": "L2 cache lines in I state filling L2",
78 "PublicDescription": "L2 cache lines in I state filling L2.",
83 "BriefDescription": "L2 cache lines in S state filling L2",
86 "PublicDescription": "L2 cache lines in S state filling L2.",
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/ivytown/
Dcache.json46 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
53 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
56 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
61 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
64 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
69 …"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-reject…
77 "BriefDescription": "L2 cache lines filling L2",
80 "PublicDescription": "L2 cache lines filling L2.",
85 "BriefDescription": "L2 cache lines in E state filling L2",
88 "PublicDescription": "L2 cache lines in E state filling L2.",
[all …]

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