| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 92 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
114 nvidia,lp0-vec:
117 <start length> Starting address and length of LP0 vector.
118 The LP0 vector contains the warm boot code that is executed
119 by AVP when resuming from the LP0 state.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.yaml | 91 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
113 nvidia,lp0-vec:
116 <start length> Starting address and length of LP0 vector.
117 The LP0 vector contains the warm boot code that is executed
118 by AVP when resuming from the LP0 state.
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| /kernel/linux/linux-5.10/arch/arm/mach-tegra/ |
| D | sleep-tegra20.S | 115 * Enters suspend in LP0 or LP1 by turning off the mmu and jumping to
242 * puts memory in self-refresh for LP0 and LP1
252 * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock
294 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
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| D | sleep-tegra30.S | 37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
232 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
246 * LP0 / LP1 use physical address, since the MMU needs to be
600 * puts memory in self-refresh for LP0 and LP1
610 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
689 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
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| D | pm.c | 261 * copy these code to IRAM before LP0/LP1 suspend and restore the content
343 [TEGRA_SUSPEND_LP0] = "LP0",
418 "self-refresh -- LP0/LP1 unavailable\n", in tegra_init_suspend()
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| D | reset-handler.S | 27 * an LP2 transition. Also branched to by LP0 and LP1 resume after
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| /kernel/linux/linux-6.6/arch/arm/mach-tegra/ |
| D | sleep-tegra20.S | 140 * Enters suspend in LP0 or LP1 by turning off the mmu and jumping to
267 * puts memory in self-refresh for LP0 and LP1
277 * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock
323 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
|
| D | sleep-tegra30.S | 37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
281 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
295 * LP0 / LP1 use physical address, since the MMU needs to be
648 * puts memory in self-refresh for LP0 and LP1
658 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
745 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
|
| D | pm.c | 261 * copy these code to IRAM before LP0/LP1 suspend and restore the content
343 [TEGRA_SUSPEND_LP0] = "LP0",
418 "self-refresh -- LP0/LP1 unavailable\n", in tegra_pm_init_suspend()
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| D | reset-handler.S | 29 * an LP2 transition. Also branched to by LP0 and LP1 resume after
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/ |
| D | parport.rst | 221 Both the above examples would inform lp that you want ``/dev/lp0`` to be
226 name, so ``/dev/lp0`` was always the port at 0x3bc. This is no longer the
227 case - if you only have one port, it will default to being ``/dev/lp0``,
|
| D | serial-console.rst | 25 lp0 for the first parallel port
|
| /kernel/linux/linux-5.10/Documentation/admin-guide/ |
| D | parport.rst | 221 Both the above examples would inform lp that you want ``/dev/lp0`` to be
226 name, so ``/dev/lp0`` was always the port at 0x3bc. This is no longer the
227 case - if you only have one port, it will default to being ``/dev/lp0``,
|
| D | serial-console.rst | 25 lp0 for the first parallel port
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| /kernel/linux/linux-6.6/arch/arm/include/asm/mach/ |
| D | arch.h | 40 unsigned char reserve_lp0 :1; /* never has lp0 */
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| /kernel/linux/linux-5.10/arch/arm/include/asm/mach/ |
| D | arch.h | 40 unsigned char reserve_lp0 :1; /* never has lp0 */
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| /kernel/linux/linux-6.6/drivers/char/ |
| D | lp.c | 44 * lp=parport1,none,parport2 (bind lp0 to parport1, disable lp1 and
71 * lp0 0x3bc
77 * to lp0 regardless of its I/O address. If you need the old behaviour, you
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| /kernel/linux/linux-5.10/drivers/char/ |
| D | lp.c | 44 * lp=parport1,none,parport2 (bind lp0 to parport1, disable lp1 and
71 * lp0 0x3bc
77 * to lp0 regardless of its I/O address. If you need the old behaviour, you
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | i9xx_wm.c | 2552 * and thus fail gracefully if LP0 watermarks in ilk_validate_wm_level()
2649 /* ILK primary LP0 latency is 700 ns */ in ilk_read_wm_latency()
2658 /* ILK sprite LP0 latency is 1300 ns */ in intel_fixup_spr_wm_latency()
2666 /* ILK cursor LP0 latency is 1300 ns */ in intel_fixup_cur_wm_latency()
2767 /* LP0 watermark maximums depend on this pipe alone */ in ilk_validate_pipe_wm()
2775 /* LP0 watermarks always use 1/2 DDB partitioning */ in ilk_validate_pipe_wm()
2778 /* At least LP0 must be valid */ in ilk_validate_pipe_wm()
2780 drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n"); in ilk_validate_pipe_wm()
3069 /* LP0 register values */ in ilk_compute_wm_results()
3360 * For active pipes LP0 watermark is marked as in ilk_pipe_wm_get_hw_state()
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| /kernel/linux/linux-5.10/drivers/soc/tegra/ |
| D | pmc.c | 61 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
330 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
363 * @lp0_vec_phys: physical base address of the LP0 warm boot code
364 * @lp0_vec_size: size of the LP0 warm boot code
1645 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
2796 "LP0"
3084 "LP0",
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| /kernel/linux/linux-6.6/arch/arm/kernel/ |
| D | setup.c | 209 #define lp0 io_res[0] macro
921 * possessing lp0, lp1 or lp2 in request_standard_resources()
924 request_resource(&ioport_resource, &lp0); in request_standard_resources()
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| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | setup.c | 216 #define lp0 io_res[0] macro
914 * possessing lp0, lp1 or lp2 in request_standard_resources()
917 request_resource(&ioport_resource, &lp0); in request_standard_resources()
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| /kernel/linux/linux-5.10/Documentation/usb/ |
| D | gadget-testing.rst | 868 If udev is active, then e.g. /dev/usb/lp0 should appear.
878 # cat > /dev/usb/lp0
886 # cat /dev/usb/lp0
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| /kernel/linux/linux-6.6/drivers/soc/tegra/ |
| D | regulators-tegra30.c | 372 * hardware for resuming from LP0. in tegra30_regulator_prepare_suspend()
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| /kernel/linux/linux-5.10/arch/arm/mach-ebsa110/ |
| D | io.c | 189 * f0000de0 - f0000dfc 378 - 37f lp0
|