| /kernel/linux/linux-6.6/drivers/phy/freescale/ |
| D | phy-fsl-lynx-28g.c | 24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
45 /* Per SerDes lane registers */
46 /* Lane a General Control Register */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
55 /* Lane a Tx Reset Control Register */
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
61 /* Lane a Tx General Control Register */
62 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
71 #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) argument
73 /* Lane a Rx Reset Control Register */
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| /kernel/linux/linux-6.6/drivers/phy/marvell/ |
| D | phy-mvebu-cp110-comphy.c | 129 * A lane is described by the following bitfields:
182 unsigned lane; member
190 .lane = _lane, \
200 .lane = _lane, \
209 /* lane 0 */
214 /* lane 1 */
221 /* lane 2 */
230 /* lane 3 */
237 /* lane 4 */
250 /* lane 5 */
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| D | phy-mvebu-a3700-comphy.c | 40 * When accessing common PHY lane registers directly, we need to shift by 1,
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
227 unsigned int lane; member
234 .lane = _lane, \
246 /* lane 0 */
251 /* lane 1 */
256 /* lane 2 */
387 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */
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| D | phy-armada38x-comphy.c | 47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
59 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
61 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
67 conf |= BIT(lane->port); in a38x_set_conf()
69 conf &= ~BIT(lane->port); in a38x_set_conf()
74 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
79 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
80 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
83 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
86 a38x_comphy_set_reg(lane, COMPHY_CFG1, in a38x_comphy_set_speed()
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| /kernel/linux/linux-5.10/drivers/phy/marvell/ |
| D | phy-mvebu-cp110-comphy.c | 128 * A lane is described by the following bitfields:
180 unsigned lane; member
188 .lane = _lane, \
198 .lane = _lane, \
207 /* lane 0 */
212 /* lane 1 */
219 /* lane 2 */
227 /* lane 3 */
234 /* lane 4 */
245 /* lane 5 */
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| D | phy-mvebu-a3700-comphy.c | 58 unsigned int lane; member
67 .lane = _lane, \
81 /* lane 0 */
88 /* lane 1 */
95 /* lane 2 */
110 static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane, in mvebu_a3700_comphy_smc() argument
116 arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); in mvebu_a3700_comphy_smc()
129 static int mvebu_a3700_comphy_get_fw_mode(int lane, int port, in mvebu_a3700_comphy_get_fw_mode() argument
140 if (mvebu_a3700_comphy_modes[i].lane == lane && in mvebu_a3700_comphy_get_fw_mode()
156 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_set_mode() local
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| D | phy-armada38x-comphy.c | 46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
60 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
66 conf |= BIT(lane->port); in a38x_set_conf()
68 conf &= ~BIT(lane->port); in a38x_set_conf()
73 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
78 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
79 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
82 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
85 a38x_comphy_set_reg(lane, COMPHY_CFG1, in a38x_comphy_set_speed()
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| /kernel/linux/linux-6.6/drivers/net/dsa/b53/ |
| D | b53_serdes.c | 42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config() local
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| /kernel/linux/linux-5.10/drivers/net/dsa/b53/ |
| D | b53_serdes.c | 37 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
39 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
42 WARN_ON(lane > 1); in b53_serdes_set_lane()
45 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
46 dev->serdes_lane = lane; in b53_serdes_set_lane()
49 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
52 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
56 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
59 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
66 u8 lane = b53_serdes_map_lane(dev, port); in b53_serdes_config() local
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| /kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/ |
| D | serdes.c | 37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
41 return mv88e6xxx_phy_read(chip, lane, reg_c45, val); in mv88e6390_serdes_read()
45 int lane, int device, int reg, u16 val) in mv88e6390_serdes_write() argument
49 return mv88e6xxx_phy_write(chip, lane, reg_c45, val); in mv88e6390_serdes_write()
98 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, in mv88e6352_serdes_power() argument
120 u8 lane, unsigned int mode, in mv88e6352_serdes_pcs_config() argument
169 u8 lane, struct phylink_link_state *state) in mv88e6352_serdes_pcs_get_state() argument
190 u8 lane) in mv88e6352_serdes_pcs_an_restart() argument
203 u8 lane, int speed, int duplex) in mv88e6352_serdes_pcs_link_up() argument
236 u8 lane = 0; in mv88e6352_serdes_get_lane() local
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| D | serdes.h | 81 u8 lane, unsigned int mode,
85 u8 lane, unsigned int mode,
89 u8 lane, struct phylink_link_state *state);
91 u8 lane, struct phylink_link_state *state);
93 u8 lane);
95 u8 lane);
97 u8 lane, int speed, int duplex);
99 u8 lane, int speed, int duplex);
104 int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
106 int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| D | link_dp_training_fixed_vs_pe_retimer.c | 52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
80 uint8_t lane = 0; in dp_fixed_vs_pe_set_retimer_lane_settings() local
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
84 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
86 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
106 uint8_t lane = 0; in perform_fixed_vs_pe_nontransparent_training_sequence() local
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| D | link_dp_training.c | 305 uint32_t lane; in maximize_lane_settings() local
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings()
314 if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING) in maximize_lane_settings()
315 max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING; in maximize_lane_settings()
317 if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS) in maximize_lane_settings()
318 max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS; in maximize_lane_settings()
319 if (lane_settings[lane].FFE_PRESET.settings.level > in maximize_lane_settings()
322 lane_settings[lane].FFE_PRESET.settings.level; in maximize_lane_settings()
343 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in maximize_lane_settings()
344 lane_settings[lane].VOLTAGE_SWING = max_requested.VOLTAGE_SWING; in maximize_lane_settings()
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| /kernel/linux/linux-6.6/drivers/phy/tegra/ |
| D | xusb.c | 115 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, in tegra_xusb_lane_parse_dt() argument
118 struct device *dev = &lane->pad->dev; in tegra_xusb_lane_parse_dt()
126 err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); in tegra_xusb_lane_parse_dt()
128 dev_err(dev, "invalid function \"%s\" for lane \"%pOFn\"\n", in tegra_xusb_lane_parse_dt()
133 lane->function = err; in tegra_xusb_lane_parse_dt()
141 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_xusb_lane_destroy() local
143 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
191 struct phy *lane; in tegra_xusb_pad_register() local
199 pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), in tegra_xusb_pad_register()
208 struct tegra_xusb_lane *lane; in tegra_xusb_pad_register() local
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| D | xusb-tegra124.c | 292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
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| D | xusb-tegra210.c | 447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable() local
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb3-ss"); in tegra210_sata_uphy_enable()
1058 static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra210_usb3_enable_phy_sleepwalk() argument
1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_sleepwalk()
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| D | xusb.h | 55 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
76 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
86 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
105 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
107 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
115 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
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| /kernel/linux/linux-6.6/drivers/platform/x86/intel/pmc/ |
| D | spt.c | 22 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
23 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
24 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
25 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
26 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
27 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
28 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
29 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
30 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
31 {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/ |
| D | onnn,nb7vpq904m.yaml | 54 An array of physical data lane indexes. Position determines how
57 Lane number represents the following
58 - 0 is RX2 lane
59 - 1 is TX2 lane
60 - 2 is TX1 lane
61 - 3 is RX1 lane
72 - Port A to RX2 lane
73 - Port B to TX2 lane
74 - Port C to TX1 lane
75 - Port D to RX1 lane
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| /kernel/linux/linux-6.6/drivers/net/dsa/mv88e6xxx/ |
| D | serdes.c | 37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
39 return mv88e6xxx_phy_read_c45(chip, lane, device, reg, val); in mv88e6390_serdes_read()
244 int lane = -ENODEV; in mv88e6341_serdes_get_lane() local
251 lane = MV88E6341_PORT5_LANE; in mv88e6341_serdes_get_lane()
255 return lane; in mv88e6341_serdes_get_lane()
261 int lane = -ENODEV; in mv88e6390_serdes_get_lane() local
268 lane = MV88E6390_PORT9_LANE0; in mv88e6390_serdes_get_lane()
274 lane = MV88E6390_PORT10_LANE0; in mv88e6390_serdes_get_lane()
278 return lane; in mv88e6390_serdes_get_lane()
286 int lane = -ENODEV; in mv88e6390x_serdes_get_lane() local
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| /kernel/linux/linux-5.10/drivers/phy/tegra/ |
| D | xusb-tegra124.c | 292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
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| /kernel/linux/linux-5.10/drivers/phy/ |
| D | phy-xgene.c | 267 /* PHY lane CSR accessing from SDS indirectly */
519 u32 speed[MAX_LANE]; /* Index for override parameter per lane */
657 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
663 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
672 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
677 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
683 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
688 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
690 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
693 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
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| /kernel/linux/linux-6.6/drivers/phy/ |
| D | phy-xgene.c | 268 /* PHY lane CSR accessing from SDS indirectly */
520 u32 speed[MAX_LANE]; /* Index for override parameter per lane */
658 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
664 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
673 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
678 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
684 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
689 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
691 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
694 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | intel_cx0_phy_regs.h | 15 #define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
19 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
30 #define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
34 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
84 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) argument
85 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) argument
86 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) argument
91 #define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \ argument
122 #define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4)) argument
123 #define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4)) argument
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | video-interfaces.yaml | 164 # Assume up to 9 physical lane indices
167 An array of physical data lane indexes. Position of an entry determines
168 the logical lane number, while the value of an entry indicates physical
169 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
170 assuming the clock lane is on hardware lane 0. If the hardware does not
171 support lane reordering, monotonically incremented values shall be used
173 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
177 # Assume up to 9 physical lane indices
180 Physical clock lane index. Position of an entry determines the logical
181 lane number, while the value of an entry indicates physical lane, e.g. for
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