| /kernel/liteos_m/arch/risc-v/nuclei/gcc/ |
| D | los_dispatch.S | 84 LOAD t1, 0x0(t0)
85 LOAD sp, 0(t1)
86 //LOAD sp, 0x0(sp) /* Read sp from first TCB member */
89 LOAD t0, 0 * REGBYTES(sp)
92 LOAD t0, (portRegNum - 1) * REGBYTES(sp)
96 LOAD x1, 1 * REGBYTES(sp) /* RA */
97 LOAD x5, 2 * REGBYTES(sp)
98 LOAD x6, 3 * REGBYTES(sp)
99 LOAD x7, 4 * REGBYTES(sp)
100 LOAD x8, 5 * REGBYTES(sp)
[all …]
|
| /kernel/linux/linux-5.10/tools/testing/selftests/powerpc/ptrace/ |
| D | ptrace-vsx.h | 11 * unsigned long load[128]
13 int validate_vsx(unsigned long *vsx, unsigned long *load) in validate_vsx() argument
18 if (vsx[i] != load[2 * i + 1]) { in validate_vsx()
19 printf("vsx[%d]: %lx load[%d] %lx\n", in validate_vsx()
20 i, vsx[i], 2 * i + 1, load[2 * i + 1]); in validate_vsx()
29 * unsigned long load[128]
31 int validate_vmx(unsigned long vmx[][2], unsigned long *load) in validate_vmx() argument
37 if ((vmx[i][0] != load[64 + 2 * i]) || in validate_vmx()
38 (vmx[i][1] != load[65 + 2 * i])) { in validate_vmx()
39 printf("vmx[%d][0]: %lx load[%d] %lx\n", in validate_vmx()
[all …]
|
| /kernel/linux/linux-6.6/tools/testing/selftests/powerpc/ptrace/ |
| D | ptrace-vsx.h | 11 * unsigned long load[128]
13 int validate_vsx(unsigned long *vsx, unsigned long *load) in validate_vsx() argument
18 if (vsx[i] != load[2 * i + 1]) { in validate_vsx()
19 printf("vsx[%d]: %lx load[%d] %lx\n", in validate_vsx()
20 i, vsx[i], 2 * i + 1, load[2 * i + 1]); in validate_vsx()
29 * unsigned long load[128]
31 int validate_vmx(unsigned long vmx[][2], unsigned long *load) in validate_vmx() argument
37 if ((vmx[i][0] != load[64 + 2 * i]) || in validate_vmx()
38 (vmx[i][1] != load[65 + 2 * i])) { in validate_vmx()
39 printf("vmx[%d][0]: %lx load[%d] %lx\n", in validate_vmx()
[all …]
|
| /kernel/linux/linux-5.10/arch/sparc/lib/ |
| D | M7memcpy.S | 48 * load words, shift half words, store words; branch to finish_up
50 * load words, shift 3 bytes, store words; branch to finish_up
52 * load words, shift 1 byte, store words; branch to finish_up
116 #ifndef LOAD
117 #define LOAD(type,addr,dest) type [addr], dest macro
209 EX_LD(LOAD(ldub, %o4, %o4), memcpy_retl_o2_plus_o5) ! load one byte
236 EX_LD(LOAD(ldx, %o1, %o4), memcpy_retl_o2_plus_63) ! load
239 EX_LD(LOAD(ldx, %o1+8, %o3), memcpy_retl_o2_plus_63_56) ! a block of 64
241 EX_LD(LOAD(ldx, %o1+16, %o4), memcpy_retl_o2_plus_63_48)
243 EX_LD(LOAD(ldx, %o1+24, %o3), memcpy_retl_o2_plus_63_40)
[all …]
|
| D | U3memcpy.S | 40 #ifndef LOAD
41 #define LOAD(type,addr,dest) type [addr], dest macro
215 EX_LD_FP(LOAD(ldub, %o1 + 0x00, %o3), U3_retl_o2_plus_g2_plus_g1_plus_1)
227 EX_LD_FP(LOAD(ldd, %o1, %f4), U3_retl_o2_plus_g2)
228 1: EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f6), U3_retl_o2_plus_g2)
236 EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f4), U3_retl_o2_plus_g2)
244 3: LOAD(prefetch, %o1 + 0x000, #one_read)
245 LOAD(prefetch, %o1 + 0x040, #one_read)
247 LOAD(prefetch, %o1 + 0x080, #one_read)
248 LOAD(prefetch, %o1 + 0x0c0, #one_read)
[all …]
|
| D | NG4memcpy.S | 65 #ifndef LOAD
66 #define LOAD(type,addr,dest) type [addr], dest macro
130 1: EX_LD(LOAD(ldub, %o1 + 0x00, %g2), memcpy_retl_o2_plus_g1)
137 51: LOAD(prefetch, %o1 + 0x040, #n_reads_strong)
138 LOAD(prefetch, %o1 + 0x080, #n_reads_strong)
139 LOAD(prefetch, %o1 + 0x0c0, #n_reads_strong)
140 LOAD(prefetch, %o1 + 0x100, #n_reads_strong)
141 LOAD(prefetch, %o1 + 0x140, #n_reads_strong)
142 LOAD(prefetch, %o1 + 0x180, #n_reads_strong)
143 LOAD(prefetch, %o1 + 0x1c0, #n_reads_strong)
[all …]
|
| D | csum_copy.S | 27 #ifndef LOAD
28 #define LOAD(type,addr,dest) type [addr], dest macro
50 EX_LD(LOAD(ldub, %o0 + 0x00, %o4))
60 EX_LD(LOAD(lduh, %o0 + 0x00, %o5))
72 LOAD(prefetch, %o0 + 0x000, #n_reads)
78 LOAD(prefetch, %o0 + 0x040, #n_reads)
91 LOAD(prefetch, %o0 + 0x080, #n_reads)
94 LOAD(prefetch, %o0 + 0x0c0, #n_reads)
97 LOAD(prefetch, %o0 + 0x100, #n_reads)
105 LOAD(prefetch, %o0 + 0x140, #n_reads)
[all …]
|
| D | NG2memcpy.S | 50 #ifndef LOAD
51 #define LOAD(type,addr,dest) type [addr], dest macro
141 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1)
143 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
144 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1);
146 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
147 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
148 EX_LD_FP(LOAD(ldd, base + 0x10, %x2), NG2_retl_o2_plus_g1);
150 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
151 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
[all …]
|
| /kernel/linux/linux-6.6/arch/sparc/lib/ |
| D | M7memcpy.S | 48 * load words, shift half words, store words; branch to finish_up
50 * load words, shift 3 bytes, store words; branch to finish_up
52 * load words, shift 1 byte, store words; branch to finish_up
116 #ifndef LOAD
117 #define LOAD(type,addr,dest) type [addr], dest macro
209 EX_LD(LOAD(ldub, %o4, %o4), memcpy_retl_o2_plus_o5) ! load one byte
236 EX_LD(LOAD(ldx, %o1, %o4), memcpy_retl_o2_plus_63) ! load
239 EX_LD(LOAD(ldx, %o1+8, %o3), memcpy_retl_o2_plus_63_56) ! a block of 64
241 EX_LD(LOAD(ldx, %o1+16, %o4), memcpy_retl_o2_plus_63_48)
243 EX_LD(LOAD(ldx, %o1+24, %o3), memcpy_retl_o2_plus_63_40)
[all …]
|
| D | U3memcpy.S | 40 #ifndef LOAD
41 #define LOAD(type,addr,dest) type [addr], dest macro
215 EX_LD_FP(LOAD(ldub, %o1 + 0x00, %o3), U3_retl_o2_plus_g2_plus_g1_plus_1)
227 EX_LD_FP(LOAD(ldd, %o1, %f4), U3_retl_o2_plus_g2)
228 1: EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f6), U3_retl_o2_plus_g2)
236 EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f4), U3_retl_o2_plus_g2)
244 3: LOAD(prefetch, %o1 + 0x000, #one_read)
245 LOAD(prefetch, %o1 + 0x040, #one_read)
247 LOAD(prefetch, %o1 + 0x080, #one_read)
248 LOAD(prefetch, %o1 + 0x0c0, #one_read)
[all …]
|
| D | NG4memcpy.S | 65 #ifndef LOAD
66 #define LOAD(type,addr,dest) type [addr], dest macro
130 1: EX_LD(LOAD(ldub, %o1 + 0x00, %g2), memcpy_retl_o2_plus_g1)
137 51: LOAD(prefetch, %o1 + 0x040, #n_reads_strong)
138 LOAD(prefetch, %o1 + 0x080, #n_reads_strong)
139 LOAD(prefetch, %o1 + 0x0c0, #n_reads_strong)
140 LOAD(prefetch, %o1 + 0x100, #n_reads_strong)
141 LOAD(prefetch, %o1 + 0x140, #n_reads_strong)
142 LOAD(prefetch, %o1 + 0x180, #n_reads_strong)
143 LOAD(prefetch, %o1 + 0x1c0, #n_reads_strong)
[all …]
|
| D | csum_copy.S | 27 #ifndef LOAD
28 #define LOAD(type,addr,dest) type [addr], dest macro
50 EX_LD(LOAD(ldub, %o0 + 0x00, %o4))
60 EX_LD(LOAD(lduh, %o0 + 0x00, %o5))
72 LOAD(prefetch, %o0 + 0x000, #n_reads)
78 LOAD(prefetch, %o0 + 0x040, #n_reads)
91 LOAD(prefetch, %o0 + 0x080, #n_reads)
94 LOAD(prefetch, %o0 + 0x0c0, #n_reads)
97 LOAD(prefetch, %o0 + 0x100, #n_reads)
105 LOAD(prefetch, %o0 + 0x140, #n_reads)
[all …]
|
| D | NG2memcpy.S | 50 #ifndef LOAD
51 #define LOAD(type,addr,dest) type [addr], dest macro
141 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1)
143 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
144 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1);
146 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
147 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
148 EX_LD_FP(LOAD(ldd, base + 0x10, %x2), NG2_retl_o2_plus_g1);
150 EX_LD_FP(LOAD(ldd, base + 0x00, %x0), NG2_retl_o2_plus_g1); \
151 EX_LD_FP(LOAD(ldd, base + 0x08, %x1), NG2_retl_o2_plus_g1); \
[all …]
|
| /kernel/linux/linux-6.6/arch/alpha/include/asm/ |
| D | xor.h | 73 xor $0,$1,$0 # 7 cycles from $1 load \n\
130 xor $0,$1,$1 # 8 cycles from $0 load \n\
131 xor $3,$4,$4 # 6 cycles from $4 load \n\
132 xor $6,$7,$7 # 6 cycles from $7 load \n\
133 xor $21,$22,$22 # 5 cycles from $22 load \n\
135 xor $1,$2,$2 # 9 cycles from $2 load \n\
136 xor $24,$25,$25 # 5 cycles from $25 load \n\
138 xor $4,$5,$5 # 6 cycles from $5 load \n\
141 xor $7,$20,$20 # 7 cycles from $20 load \n\
143 xor $22,$23,$23 # 7 cycles from $23 load \n\
[all …]
|
| /kernel/linux/linux-5.10/arch/alpha/include/asm/ |
| D | xor.h | 54 xor $0,$1,$0 # 7 cycles from $1 load \n\
111 xor $0,$1,$1 # 8 cycles from $0 load \n\
112 xor $3,$4,$4 # 6 cycles from $4 load \n\
113 xor $6,$7,$7 # 6 cycles from $7 load \n\
114 xor $21,$22,$22 # 5 cycles from $22 load \n\
116 xor $1,$2,$2 # 9 cycles from $2 load \n\
117 xor $24,$25,$25 # 5 cycles from $25 load \n\
119 xor $4,$5,$5 # 6 cycles from $5 load \n\
122 xor $7,$20,$20 # 7 cycles from $20 load \n\
124 xor $22,$23,$23 # 7 cycles from $23 load \n\
[all …]
|
| /kernel/linux/linux-5.10/tools/power/cpupower/bench/ |
| D | README-BENCH | 9 - Identify average reaction time of a governor to CPU load changes
34 You can specify load (100% CPU load) and sleep (0% CPU load) times in us which
38 load=25000
41 This part of the configuration file will create 25ms load/sleep turns,
48 Will increase load and sleep time by 25ms 5 times.
50 25ms load/sleep time repeated 20 times (cycles).
51 50ms load/sleep time repeated 20 times (cycles).
53 100ms load/sleep time repeated 20 times (cycles).
69 100% CPU load (load) | 0 % CPU load (sleep) | round
76 In round 1, ondemand should have rather static 50% load and probably
[all …]
|
| /kernel/linux/linux-6.6/tools/power/cpupower/bench/ |
| D | README-BENCH | 9 - Identify average reaction time of a governor to CPU load changes
34 You can specify load (100% CPU load) and sleep (0% CPU load) times in us which
38 load=25000
41 This part of the configuration file will create 25ms load/sleep turns,
48 Will increase load and sleep time by 25ms 5 times.
50 25ms load/sleep time repeated 20 times (cycles).
51 50ms load/sleep time repeated 20 times (cycles).
53 100ms load/sleep time repeated 20 times (cycles).
69 100% CPU load (load) | 0 % CPU load (sleep) | round
76 In round 1, ondemand should have rather static 50% load and probably
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | memory.json | 5 …p (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst …
6 …this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,…
11 …fDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
12 …Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load"
17 … was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
23 …tion": "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
29 …as reloaded from a memory location including L4 from local remote or distant due to a demand load",
35 …ache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
41 … was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
47 …Description": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
[all …]
|
| D | marked.json | 35 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
41 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
47 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
53 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
59 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
65 …cles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
71 … was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
77 …les to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
83 …fDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load",
95 …"Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | memory.json | 5 …p (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst …
6 …this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,…
11 …fDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
12 …Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load"
17 … was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
23 …tion": "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
29 …as reloaded from a memory location including L4 from local remote or distant due to a demand load",
35 …ache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
41 … was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
47 …Description": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
[all …]
|
| D | marked.json | 35 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
41 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
47 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
53 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
59 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
65 …cles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
71 … was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
77 …les to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
83 …fDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load",
95 …"Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
[all …]
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | hp_sdc.h | 175 #define HP_SDC_CMD_LOAD_RT 0x31 /* Load real time (from 8042) */
176 #define HP_SDC_CMD_LOAD_FHS 0x36 /* Load the fast handshake timer */
177 #define HP_SDC_CMD_LOAD_MT 0x38 /* Load the match timer */
178 #define HP_SDC_CMD_LOAD_DT 0x3B /* Load the delay timer */
179 #define HP_SDC_CMD_LOAD_CT 0x3E /* Load the cycle timer */
187 #define HP_SDC_CMD_READ_RAM 0x00 /* Load from i8042 RAM (autoinc) */
188 #define HP_SDC_CMD_READ_USE 0x02 /* Undocumented! Load from usage reg */
189 #define HP_SDC_CMD_READ_IM 0x04 /* Load current interrupt mask */
190 #define HP_SDC_CMD_READ_KCC 0x11 /* Load primary kbd config code */
191 #define HP_SDC_CMD_READ_KLC 0x12 /* Load primary kbd language code */
[all …]
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | hp_sdc.h | 175 #define HP_SDC_CMD_LOAD_RT 0x31 /* Load real time (from 8042) */
176 #define HP_SDC_CMD_LOAD_FHS 0x36 /* Load the fast handshake timer */
177 #define HP_SDC_CMD_LOAD_MT 0x38 /* Load the match timer */
178 #define HP_SDC_CMD_LOAD_DT 0x3B /* Load the delay timer */
179 #define HP_SDC_CMD_LOAD_CT 0x3E /* Load the cycle timer */
187 #define HP_SDC_CMD_READ_RAM 0x00 /* Load from i8042 RAM (autoinc) */
188 #define HP_SDC_CMD_READ_USE 0x02 /* Undocumented! Load from usage reg */
189 #define HP_SDC_CMD_READ_IM 0x04 /* Load current interrupt mask */
190 #define HP_SDC_CMD_READ_KCC 0x11 /* Load primary kbd config code */
191 #define HP_SDC_CMD_READ_KLC 0x12 /* Load primary kbd language code */
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| D | pipeline.json | 27 …re is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded",
30 …ere is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded"
33 …due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles…
36 …due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles…
39 …truction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded",
42 …struction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded"
45 …peration issued due to the backend, load.This event counts every cycle there is a stall in the Wr …
48 …peration issued due to the backend, load.This event counts every cycle there is a stall in the Wr …
57 …on issued due to the backend, load, cache miss.This event counts every cycle there is a stall in t…
60 …on issued due to the backend, load, cache miss.This event counts every cycle there is a stall in t…
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/alderlaken/ |
| D | memory.json | 3 …load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, …
10 …dest load) of the load buffer is stalled due to a core bound stall including a store address match…
17 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
24 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
27 …"PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer a…
32 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
39 …"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer an…
|